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t6022-j475d: enable die-0 dcpext2/3, five displays on the M2 Ultra Mac Studio - #467

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Five displays on the Mac Studio (M2 Ultra, J475d): four on the rear USB-C ports plus HDMI. Stacked on #463 (itself on #462): please review only the last commit, arm64: dts: apple: t6022-j475d: add die-0 dcpext2/3 for the rear ports.

Problem

Die 0 of the t6022 is the M2 Max die, with four external DCPs (dcpext0–dcpext3 in the ADT). The J475d tree enables only dcpext0 and dcpext1 for its four rear USB-C ports (HDMI runs from die 1), so a third USB-C display waits for a free pipeline and stays dark.

Change

  • t6021-display2.dtsi already adds dcpext2/dcpext3 (crossbar states 4 and 6) for the 14/16-inch M2 Max. It gets a DISPLAY2_SOC parent macro, which defaults to &{/soc}, so it can be placed under &die0 on t6022.
  • t6022-j475d.dts includes it under &die0 and extends both DCPs to the fourth rear port: atcphy3, atcphy3_xbar, route@3, and endpoint@2/@3 on typec3's port@3. It sets &display iommus to the J475d list (die-1 HDMI DART first) plus dispext2_dart/dispext3_dart.

dcpext2/dcpext3 are DP-alt candidates only (typecN on crossbar cell 0). Thunderbolt DPIN stays on the dcpext0/dcpext1 pairs from #463.

The macOS ADT on this machine matches the laptop nodes: dcpext2@8DC00000 and dcpext3@DC00000, dart-dcpext2@8D30C000, mailbox interrupts 0x413–0x416 (1043–1046) and 0x437–0x43a (1079–1082), DART interrupt 0x3fe (1022). The aliases (dcpext2, dcpext3) match the ADT indices, which m1n1 needs to fill apple,firmware-compat.

Device tree check

Built with the kernel's own scripts/dtc:

  • t6021-j414c and t6021-j416c (the other users of t6021-display2.dtsi) are byte-identical before and after.
  • On t6022-j475d, all four die-0 DCPs (289c00000, 315c00000, 48dc00000, 50dc00000) carry route@0–route@3, and each rear typecN port@3 has four endpoints. checkpatch --strict is clean.

Hardware testing

Mac Studio (M2 Ultra, 2023), apple,j475d. Stock linux-aurora 7.2.11.aurora16-1 kernel plus #463's two rebuilt modules, with this branch's J475d dtb. m1n1 stage 2 is omacom/m1n1#48. OS firmware 13.5, system firmware 26.6.2.

All five DCPs bind and boot:

apple-dcp 48dc00000.dcp: DCP index:3 dptx target phy: 1 dptx die: 0
apple-drm soc@200000000:display-subsystem: bound 48dc00000.dcp (ops dcp_comp_ops [appledrm])
apple-dcp 50dc00000.dcp: DCP index:4 dptx target phy: 1 dptx die: 0
apple-drm soc@200000000:display-subsystem: bound 50dc00000.dcp (ops dcp_comp_ops [appledrm])
apple-dcp 289c00000.dcp: DCP booted
apple-dcp 315c00000.dcp: DCP booted
apple-dcp 48dc00000.dcp: DCP booted
apple-dcp 50dc00000.dcp: DCP booted
apple-dcp 2289c00000.dcp: DCP booted

Five displays at once:

Display Connection DCP Mode
Dell U2718Q HDMI dcpext4 (die 1) 3840x2160@60
LG 40WP95C Thunderbolt, rear dcpext1 5120x2160@72
Dell U2417H USB-C to DP cable, rear dcpext2 1920x1080@60
Portable 3840x2400 panel USB-C direct, rear dcpext3 3840x2400@60
LG UltraFine 4K USB-C to DP cable, rear dcpext0 3840x2160@60
apple-display-crossbar f0304c000.mux: Switched dpphy to dispext2,0
apple-dcp 48dc00000.dcp: set_digital_out_mode(color:94 timing:65) "1920x1080": 60 ...
apple-display-crossbar b0304c000.mux: Switched dpphy to dispext3,0
apple-dcp 50dc00000.dcp: set_digital_out_mode(color:84 timing:43) "3840x2400": 60 ...
Action Result
Boot with three displays, the new DCPs idle pass, no change to the existing displays
Hotplug a 4th display (rear 2), then a 5th (rear 3) pass, on dcpext2 and dcpext3 in that order
Unplug/replug each display on dcpext2 and dcpext3 pass, back on the same DCP
DPMS off/on with all five lit pass, all five back. The compositor re-paired CRTCs, and routes followed: Thunderbolt to dcpext0, the portable to dcpext1, the UltraFine to dcpext3, so all four die-0 DCPs drove both DP alt and the tunnel
Thunderbolt unplug/replug while the other four hold their DCPs pass, back at 5120x2160@72 about 2.4 s after new device found

No WARNING, BUG or oops in the boot. Not tested: suspend/resume with five displays, DP audio on dcpext2/3.

Found along the way, not fixed here

A second Thunderbolt stream (dpin1, here a monitor daisy-chained behind the 40WP95C) is refused with dpin1: DP tunnel setup failed: -16. This is independent of this PR. apple_drv.c fixes each port's secondary connector to the lowest-indexed Type-C-only pipeline, which is dcpext1 on the laptops, where dcpext0 is the HDMI hybrid. On the J475d every die-0 DCP is Type-C-only, so that's dcpext0, which the dpin0 stream also prefers. The two streams collide while dcpext1/dcpext3 sit idle. I'll send that separately with a fabric change and KUnit coverage.

…ports

On the Mac Studio (M2 Ultra) no display controller is wired to the four
rear USB-C ports, so a USB-C DisplayPort display there never lights up.
The dcpext1 routes in t602x-j474-j475.dtsi sit inside the
APPLE_T602X_NON_ULTRA block together with the USB4/PCIe-C wiring, and
t6022 does not define it.

The die-0 half of the t6022 keeps the plain labels and the same rear-port
wiring as the M2 Max Studio. macOS on a J475d drives a DP alt mode display
on rear ports 1 and 2 from DCPEXT1 through the display crossbar (ADT
display-crossbar0, "display-crossbar,t602x"), the same controller the
non-Ultra boards use. Keep only the USB4 aliases, the PCIe-C tunnels and
the non-Ultra display iommus under the guard. The dcpext1 display routes,
dpaudio2, the ATC crossbars and the always-on ATC common power domains now
apply to J475d too.

t6022-jxxxd.dtsi points the display subsystem at the die-1 HDMI DART only,
so add dispext1_dart to it on J475d for the framebuffers of the new pipe.

J474s and J475c keep the same nodes and properties; only the position of
the dcpext1 alias within /aliases changes.

Signed-off-by: Jacob Crowther <3944151+jcrowthe@users.noreply.github.com>
The M2 Ultra is two t6021 dies. Its die-0 ACIO, ATC and display crossbar
are the ones the M2 Pro/Max laptops use, and the DCPs are the same
apple,t6020-dcpext. With t6022 missing from apple_dpin_qualified_soc, a
Thunderbolt display on a J475d enumerates, but the DP IN adapter never
asks for a pipeline and the tunnel is torn down after the DPRX timeout:

  thunderbolt-apple-nhi f01f00000.nhi: 0:5 <-> 1:13 (DP): not active, tearing down

Qualify t6022 with the same M2 (pre/post) flow. That flow still requires
dual-stream connector wiring, so nothing changes until a board's DT
describes it.

Tested on a Mac Studio (M2 Ultra, J475d) with an LG 40WP95C on rear
ports 1 and 2: 5120x2160@72, hotplug, and DPMS off/on.

Signed-off-by: Jacob Crowther <3944151+jcrowthe@users.noreply.github.com>
… tunnels

Qualify t6022 for the T602x tunnel clock sequence, as for the
Thunderbolt side, and accept the ATC3 core at 0x1303000000. The 14/16-inch
boards only have ATC0-2, so ATC3 was never listed, but the Mac mini and
Mac Studio use it for their fourth rear port. The wiring gate still
applies.

Tested on a Mac Studio (M2 Ultra, J475d): a DP tunnel on rear port 1
(phy@1303000000) runs 5120x2160@72.

Signed-off-by: Jacob Crowther <3944151+jcrowthe@users.noreply.github.com>
…ar ports

On M2, Thunderbolt DP tunnels need dual-stream connector wiring: two
DCPs per Type-C connector, each with typecN-dpin0/1 controls on cells 1
and 2 of the port's crossbar, as on the 14/16-inch boards. The J475d's
HDMI runs from die 1, so die-0 dcpext0 is free. Enable it as a USB-C-only
pipeline for the rear ports (crossbar state 0, dcpext1 state 2), give
both die-0 DCPs the DPIN controls, add the second endpoint to each rear
connector, and add dispext0_dart to the display iommus.

m1n1 fills apple,firmware-compat only through the ADT-indexed dcpextN
aliases. Without "dcpext0" here, probe fails with
"Could not read 'apple,firmware-compat': -22" and the whole apple-drm
aggregate stays down, HDMI included.

Tested on a Mac Studio (M2 Ultra, J475d), together with the two previous
patches: HDMI (dcpext4), a DP alt mode display on rear port 4 (dcpext0)
and a Thunderbolt display on rear port 2 (dcpext1, dpin0) all run at once.

Signed-off-by: Jacob Crowther <3944151+jcrowthe@users.noreply.github.com>
Die 0 of the t6022 is the M2 Max die, with four external DCPs, but the
J475d enables only dcpext0 and dcpext1 for its four rear USB-C ports, so
a third USB-C display waits for a free pipeline.

Reuse t6021-display2.dtsi, which adds dcpext2/3 (crossbar states 4 and
6) on the 14/16-inch M2 Max, and extend it to the fourth rear port. The
include gets a DISPLAY2_SOC parent so it can be placed under die 0 on
t6022; the laptop trees build unchanged.

The ADT on this machine matches the laptop nodes: dcpext2@8DC00000 and
dcpext3@DC00000, mailbox interrupts 1043-1046 and 1079-1082, DART
interrupt 1022.

Signed-off-by: Jacob Crowther <3944151+jcrowthe@users.noreply.github.com>
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