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Use the PMGR provider active-state predicate when checking inherited display power. DISP_CPU can report ACTUAL=4 with AUTO_ENABLE and TARGET=15 after automatic clock gating. Keep the checks read-only and preserve all other handoff requirements. Test all actual, target and automatic-state combinations and the captured J613 state through the production helper. Signed-off-by: Satya Benson <satya@benson.earth>
The 25G83 device tree advertises the AGX-specific compatible followed by asc-mailbox-v4. Both bind the same mailbox operations. Admit this exact pair while retaining all resource and identity checks. Exercise the production rejection predicate with public-DTS fixtures and resource mutations; allow optional local DT captures for reproduction. Signed-off-by: Satya Benson <satya@benson.earth>
Cross all 512 ACTUAL/TARGET/AUTO combinations with zero, all-set, alternating and individual unrelated-bit patterns. This verifies that readiness ignores every bit outside the three PMGR fields. A temporary ACTUAL mask widened from GENMASK(7, 4) to GENMASK(8, 4) passes the old cases but fails the new ones at both -O0 and -O2. Make the unoptimized compiler flag explicit and report failing words. Signed-off-by: Satya Benson <satya@benson.earth>
Signed-off-by: Satya Benson <satya@benson.earth>
…records Separate firmware identity, HAL metadata and VM bounds from physical G15G stream selection. Add checked root and owned IO descriptor encoders. Introduce slot 28 at SGX+0xd50000 with a production-writer regression; the shifted T8132 bank is never introduced. Keep VM padding zero. Signed-off-by: Satya Benson <satya@benson.earth>
Build extended initialization owners, controller images and channel records with checked allocation spans. Publish the bounded loader table through existing M3 ownership. Keep extended runtime admission closed. Signed-off-by: Satya Benson <satya@benson.earth>
Construct native queue, pool, context and notifier records. Read controller inputs from the admitted OPP handoff, preserve nanosecond durations and reject unsupported optional flags. Prepare native startup without enabling extended admission. Signed-off-by: Satya Benson <satya@benson.earth>
Dispatch extended firmware compute records through the existing M3 runtime while preserving G15 CDM streams. Retain owned pool backing and leave firmware-managed register setup to the extended interface. Signed-off-by: Satya Benson <satya@benson.earth>
Encode extended tiler and fragment work, scene records, independent notifications and attachment visibility through the existing runtime. Retire native pools and enable only the exact J613 26.6.2 profile. Keep the public UAPI and physical G15 stream formats unchanged. Signed-off-by: Satya Benson <satya@benson.earth>
Signed-off-by: Satya Benson <satya@benson.earth>
Signed-off-by: Satya Benson <satya@benson.earth>
satchlj
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maralcbr and
scottjones
as code owners
November 4, 2026 01:34
Signed-off-by: Satya Benson <satya@benson.earth>
Signed-off-by: Satya Benson <satya@benson.earth>
Signed-off-by: Satya Benson <satya@benson.earth>
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Claude Fable 5.2 on @satchlj's behalf Closing in favour of aurora-silicon/linux#977, which carried this change to aurora-silicon/linux integration/aurora and is merged. |
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GPU26 completion currently repeats four 5 us fsleep calls, which select udelay, before every bounded timer sleep. Remove those non-scheduling delays and use IRQ-assisted sleeps with 25→50→100→200→400→800→1000 us fallback backoff. Reset on publication/retirement progress rather than on every timer or firmware event; continue to snapshot immediately when an IRQ wakes the worker.
Keep all retirement witnesses, timeout/fault handling, lost-wakeup sequencing and synchronous timer cancellation. The root-only completion_wait control becomes an adaptive ceiling (version 2, default 1000 us); normal waits continue outside the runtime lock. Add deterministic host/KUnit policy coverage and an analyzer for existing GPU-end/fence timestamp logs.
Stacked on #346 at 192a39d, which includes updated GPU26 #303–#307 and the C13k MMU alias correction. The two completion-wait commits were replayed onto that public head because both touch m3_drm.rs; diagnostic C13k history was removed. Base is integration/aurora, so prerequisite stack changes remain in the displayed diff. Range-diff confirms the two patches are unchanged apart from sign-offs.
Before replay: runtime 98/98, batching 12/12 and firmware 21/21 host tests passed in debug and optimized builds; the pinned host runner passed 10 suites. The affected module compiled/linked with W=1/BTF. QEMU KUnit passed 1751 cases with 3 expected skips and no failures, including all four completion-policy cases. Those build/runtime results precede this replay; no full kernel/package or new hardware boot was performed for the rebased head. Post-replay diff checks pass. Fresh Rust 1.98.1 host runs on the public stack pass runtime 82/82 (including the four policy cases), batching 12/12 and firmware 21/21 in debug and optimized modes. The public stack has fewer runtime cases than the diagnostic C13k baseline. The subsequent rebase onto #346's manifest-only CI fix leaves source/test bytes unchanged.
C13l-r2 observed all-worker CPU of 20.44% of one core versus C13k 36.18%. C13k ran on battery/power-saver and C13l on AC/balanced, with background-session differences: causal CPU savings are not established. Fence latency remains unmeasured because the timing flag (bit 25) was absent; matched timing runs and physical-display acceptance remain open. Zero MMU/PPL/GEM_BIND errors were observed. A10 HIGH 16.53 ms versus MEDIUM 16.61 ms loaded p99 establishes no material same-boot HIGH advantage; firmware queue encoding is unchanged.