drm/asahi: G17 (Neo, T8140) driver update for 7.2.11

drivers/dma-buf/dma-fence-array.c

@@ -107,17 +107,11 @@ static bool dma_fence_array_signaled(struct dma_fence *fence)
 	unsigned int i;
 
 	/*
-	 * We need to read num_pending before checking the enable_signal bit
-	 * to avoid racing with the enable_signaling() implementation, which
-	 * might decrement the counter, and cause a partial check.
-	 * atomic_read_acquire() pairs with atomic_dec_and_test() in
-	 * dma_fence_array_enable_signaling()
-	 *
-	 * The !--num_pending check is here to account for the any_signaled case
-	 * if we race with enable_signaling(), that means the !num_pending check
-	 * in the is_signalling_enabled branch might be outdated (num_pending
-	 * might have been decremented), but that's fine. The user will get the
-	 * right value when testing again later.
+	 * Read the counter before the enable bit so callback installation
+	 * cannot make a partial count look complete. The acquire pairs with
+	 * the counter decrements in dma_fence_array_enable_signaling().
+	 * If enabling races with the lazy scan, every child must still be
+	 * observed complete before that scan can return true.
 	 */
 	num_pending = atomic_read_acquire(&array->num_pending);
 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &array->base.flags)) {
@@ -126,8 +120,16 @@ static bool dma_fence_array_signaled(struct dma_fence *fence)
 		return false;
 	}
 
+	/*
+	 * Arrays require every member to complete. A pending member already
+	 * proves the array incomplete; polling its successors only repeats work
+	 * during timeline-chain walks. Keep the completion counter and the
+	 * enabled-signaling path unchanged.
+	 */
 	for (i = 0; i < array->num_fences; ++i) {
-		if (dma_fence_is_signaled(array->fences[i]) && !--num_pending)
+		if (!dma_fence_is_signaled(array->fences[i]))
+			return false;
+		if (!--num_pending)
 			goto signal;
 	}
 	return false;
@@ -256,8 +258,7 @@ EXPORT_SYMBOL(dma_fence_array_init);
  * and fill it with the fences it wants to add to the object. Ownership of this
  * array is taken and dma_fence_put() is used on each fence on release.
  *
- * If @signal_on_any is true the fence array signals if any fence in the array
- * signals, otherwise it signals when all fences in the array signal.
+ * The array signals when every fence in the array signals.
  */
 struct dma_fence_array *dma_fence_array_create(int num_fences,
 					       struct dma_fence **fences,

drivers/dma-buf/st-dma-fence-unwrap.c

@@ -15,16 +15,26 @@
 struct mock_fence {
 	struct dma_fence base;
 	spinlock_t lock;
+	atomic_t polls;
 };
 
 static const char *mock_name(struct dma_fence *f)
 {
 	return "mock";
 }
 
+static bool mock_signaled(struct dma_fence *fence)
+{
+	struct mock_fence *f = container_of(fence, struct mock_fence, base);
+
+	atomic_inc(&f->polls);
+	return false;
+}
+
 static const struct dma_fence_ops mock_ops = {
 	.get_driver_name = mock_name,
 	.get_timeline_name = mock_name,
+	.signaled = mock_signaled,
 };
 
 static struct dma_fence *__mock_fence(u64 context, u64 seqno)
@@ -36,6 +46,7 @@ static struct dma_fence *__mock_fence(u64 context, u64 seqno)
 		return NULL;
 
 	spin_lock_init(&f->lock);
+	atomic_set(&f->polls, 0);
 	dma_fence_init(&f->base, &mock_ops, &f->lock, context, seqno);
 
 	return &f->base;
@@ -584,7 +595,71 @@ static void test_unwrap_merge_complex_seqno(struct kunit *test)
 	dma_fence_put(f1);
 }
 
+/*
+ * A pending all-of array needs no polls of later members. Keep its
+ * independent member fences so their polling and out-of-order completion
+ * remain observable without enabling callbacks on the array.
+ */
+static void test_array_pending_prefix(struct kunit *test)
+{
+	struct dma_fence *first = mock_fence(), *last = mock_fence();
+	struct dma_fence *array;
+	struct mock_fence *last_mock;
+
+	if (!first || !last) {
+		KUNIT_FAIL(test, "Could not allocate member fences");
+		goto out;
+	}
+	last_mock = container_of(last, struct mock_fence, base);
+	array = mock_array(2, dma_fence_get(first), dma_fence_get(last));
+	if (!array) {
+		KUNIT_FAIL(test, "Could not allocate fence array");
+		goto out;
+	}
+	KUNIT_EXPECT_FALSE(test, dma_fence_is_signaled(array));
+	KUNIT_EXPECT_EQ(test, atomic_read(&last_mock->polls), 0);
+	dma_fence_signal(last);
+	KUNIT_EXPECT_FALSE(test, dma_fence_is_signaled(array));
+	dma_fence_signal(first);
+	KUNIT_EXPECT_TRUE(test, dma_fence_is_signaled(array));
+	dma_fence_put(array);
+out:
+	dma_fence_put(last);
+	dma_fence_put(first);
+}
+
+static void test_array_pending_suffix(struct kunit *test)
+{
+	struct dma_fence *first = mock_fence(), *last = mock_fence();
+	struct dma_fence *array;
+
+	if (!first || !last) {
+		KUNIT_FAIL(test, "Could not allocate member fences");
+		goto out;
+	}
+	array = mock_array(2, dma_fence_get(first), dma_fence_get(last));
+	if (!array) {
+		KUNIT_FAIL(test, "Could not allocate fence array");
+		goto out;
+	}
+	dma_fence_signal(first);
+	KUNIT_EXPECT_FALSE(test, dma_fence_is_signaled(array));
+	/* Installing callbacks after a lazy partial poll must still account
+	 * for the already signaled first member and wait for the last.
+	 */
+	dma_fence_enable_signaling(array);
+	KUNIT_EXPECT_FALSE(test, dma_fence_is_signaled(array));
+	dma_fence_signal(last);
+	KUNIT_EXPECT_GT(test, dma_fence_wait_timeout(array, false, HZ), 0L);
+	dma_fence_put(array);
+out:
+	dma_fence_put(last);
+	dma_fence_put(first);
+}
+
 static struct kunit_case dma_fence_unwrap_cases[] = {
+	KUNIT_CASE(test_array_pending_prefix),
+	KUNIT_CASE(test_array_pending_suffix),
 	KUNIT_CASE(test_sanitycheck),
 	KUNIT_CASE(test_unwrap_array),
 	KUNIT_CASE(test_unwrap_chain),

drivers/gpu/drm/asahi/Makefile

@@ -1,7 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_DRM_ASAHI) += asahi.o
-asahi-y := asahi_core.o sysfs.o
+asahi-y := asahi_core.o sysfs.o g17/sync_input.o g17/sync_output.o g17/sync_scope.o g17/trace.o
+CFLAGS_g17/trace.o := -I$(src)/g17
 
 asahi-$(CONFIG_DRM_ASAHI_G15) += g15/glue.o
 asahi-$(CONFIG_DRM_ASAHI_UAT_ADOPTION) += g15/uat_glue.o

drivers/gpu/drm/asahi/asahi_core.rs

@@ -1,3 +1,3 @@
 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 #![recursion_limit = "2048"]
 
@@ -25,6 +25,7 @@
 mod hw;
 mod initdata;
 mod mem;
+mod memacct;
 mod m3;
 mod microseq;
 mod mmu;
@@ -35,6 +36,7 @@
 mod slotalloc;
 mod stats;
 mod sysfs_exports;
+mod timestamp;
 mod util;
 #[cfg(CONFIG_DRM_ASAHI_MAPLE_TREE)]
 mod vm;
@@ -172,5 +174,17 @@
             // permissions: 0,
             description: "Export AGX firmware stats to sysfs (1 = on, 0 = off)",
         },
+        mem_limit_pct: u32 {
+            default: 67,
+            description: "G17: device-wide GPU memory limit in percent of RAM (0 or >= 100: none)",
+        },
+        client_mem_limit_pct: u32 {
+            default: 50,
+            description: "G17: per-client GPU memory limit in percent of RAM (0: the device limit)",
+        },
+        oom_attribution: u8 {
+            default: 1,
+            description: "G17: count held GPU memory in its creator's RSS for the OOM killer (1 = on)",
+        },
     },
 }

drivers/gpu/drm/asahi/driver.rs

@@ -1,3 +1,3 @@
 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 
 //! Top-level GPU driver implementation.
@@ -91,6 +91,10 @@
     desc: c"Apple AGX Graphics",
 };
 
+// Open DRM files and exported DMA buffers take their callbacks' module from `MODULE`. With
+// `None`, a modular build could be unloaded while they still point into it.
+const _: () = assert!(<AsahiDrmDriver as drm::driver::Driver>::MODULE.is_some());
+
 /// DRM Driver implementation for `AsahiDriver`.
 #[vtable]
 impl drm::driver::Driver for AsahiDrmDriver {
@@ -153,6 +157,10 @@
             of::DeviceId::new(c"apple,agx-t8140"),
             ProbeConfig::G17(&hw::t8140::CONFIG)
         ),
+        (
+            of::DeviceId::new(c"apple,agx-t6040"),
+            ProbeConfig::G17(&hw::t6040::CONFIG)
+        ),
         (
             of::DeviceId::new(c"apple,agx-t8103"),
             ProbeConfig::Legacy(&hw::t8103::HWCONFIG)
@@ -390,6 +398,8 @@
         pdev: &'bound platform::Device<Core<'_>>,
         cfg: &'static g17::Config,
     ) -> Result<AsahiPlatformDriverData<'bound>> {
+        // The GPU memory limits and RSS attribution apply only to G17 for now.
+        crate::memacct::LEDGER.configure();
         // SAFETY: The GPU performs DMA through a UAT whose output width is part of the SoC config.
         unsafe { pdev.dma_set_mask_and_coherent(DmaMask::try_new(cfg.uat_oas)?)? };
         let resources = regs::Resources::new(pdev)?;
@@ -419,6 +429,11 @@
                 return Err(error);
             }
         };
+        if let Err(error) =
+            crate::sysfs_exports::register_idle(raw_dev, crate::g17::power::IDLE_HOLD_MS.as_ptr())
+        {
+            dev_warn!(pdev.as_ref(), "idle_off_delay_ms not registered: {:?}\n", error);
+        }
         Ok(AsahiPlatformDriverData {
             _device: reg.device().into(),
             _reg: reg,
@@ -433,7 +448,7 @@
 
 impl Drop for AsahiPlatformDriverData<'_> {
     fn drop(&mut self) {
-        // SAFETY: `self.raw_dev` was set in `probe` from the platform
+        // `self.raw_dev` was set in `probe` from the platform
         // device's `as_raw()`, valid for the lifetime of the bound driver.
         if !self.raw_dev.is_null() {
             crate::sysfs_exports::unregister(self.raw_dev, self.raw_stats);