Simple RISC Processor

A custom 32-bit RISC-style processor implemented from scratch in Verilog, with a full instruction set, control unit, and a self-checking testbench for every module.

Architecture

The processor is built as separate modules wired together in Processor.v (top-level module riscProcessor):

Module	File	Role
riscProcessor	Processor.v	Top-level module — wires everything together
controlUnit	ControlUnit.v	Decodes the opcode and drives every control signal (ALU op, memory read/write, register write, PC source, stack push/pop, ...)
ALU	ALU.v	Performs AND / ADD / SUB, sets zero and negative flags
registerFile	registerFile.v	16 general-purpose 32-bit registers (R0-R15)
instructionMemory	instructionMemory.v	Holds the program
dataMemory	dataMemory.v	256-word data memory, also handles stack-relative addressing
pcModule	pcModule.v	Program counter, supports sequential, jump, branch, and return targets
stackPointer	StackPointer.v	Tracks the stack pointer for PUSH/POP/CALL/RET, with empty/full flags
ClockGenerator	ClockGenerator.v	Drives the simulation clock

Every module above has a matching testbench (*_tb.v), so each piece can be verified independently before checking the full processor.

Datapath

Instruction set

Instructions are 32 bits, with a 6-bit opcode (constants.v defines all the encodings).

R-Type (register-register): AND, ADD, SUB

I-Type (register-immediate): ANDI, ADDI, LW, LWPOI (load word, post-increment), SW, and conditional branches BGT, BLT, BEQ, BNE

J-Type (jump/call): JMP, CALL (pushes return address), RET (pops return address)

S-Type (stack): PUSH, POP

Running the simulation

These files were originally simulated in Xilinx ISE, but every module also runs cleanly with the free, open-source Icarus Verilog:

# example: simulate just the ALU
iverilog -o alu_sim ALU.v ALU_tb.v
vvp alu_sim

# simulate the full processor
iverilog -o processor_sim Processor.v ControlUnit.v ALU.v registerFile.v \
    instructionMemory.v dataMemory.v pcModule.v StackPointer.v ClockGenerator.v
vvp processor_sim

Each testbench prints its results to the console via $display.

Notes

• Built for the Computer Architecture course (ENCS4370) at Birzeit University — Project #2: a multicycle datapath processor, designed and implemented from scratch, including the datapath, control unit, and full instruction set, with simulation and testing for every module.
• constants.v is the single source of truth for opcodes and control signal encodings — start there to understand how an instruction flows through the datapath.
• The full project report covers the design process end to end: building the datapath instruction type by instruction type, the control unit's state diagram, and simulation/testing results for every module.