[silvervest]

Merge order: any time: independent of the other PRs of this set (#178-#185).

Improvement.

Every diff an agent reads (compile_and_diff, last_diff; every console and mode) gets a second line: the target's instructions the candidate lacks and the other way round, among the differing rows, with register names, symbol names, stack slot offsets, branch targets and instruction order set aside; or that nothing is left once they are, which wants another approach (statement order, temporaries, types) than code that's missing.

Of 489 near misses on an x86 game with real differences left, 273 had some past the 60 rows a diff shows, behind rows that differed only by register, and 6 showed none at all.

Test: test_a_diff_says_what_differs_once_registers_and_order_are_set_aside (tests/test_diff_output.py). ruff is clean.

🤖 Generated with Claude Code

[n-delic]

Thanks. A diff that says what's left once registers, stack slots and order are set aside is a good aid, and the score and match verdict are untouched. But the residue can say there's no difference when there is one, which is the opposite of its purpose:

1. x86 prefixes hide the real opcode (scoring.py:215-216, 218-229). shape() takes only the first word as the mnemonic, so in lock add the opcode add is treated as an operand name and becomes S. Real capstone output: lock add dword ptr [eax], ecx vs lock sub dword ptr [eax], ecx gives residue == ([], []). render_rows then says "Registers, stack slots and order aside, your instructions are the target's", while the summary above says 1 different. Parse lock/rep/repe/repne/xacquire/xrelease/bnd together with the next word, and test a real prefixed pair.

2. Stack-slot normalisation also hides index scales and shift amounts (:204, :224). _NUMBER runs over the whole bracketed operand, so [esp + ecx*4 + 0x18] and [esp + ecx*8 + 0x18] both become [R+R*S+S], with an empty residue. 4 vs 8 is an element-size difference, not a frame offset. ARM's [sp, r2, lsl #2] vs lsl #3 behaves the same way. Replace only the displacement, and test both.

Please also add tests on real-shaped diffs from each arch the residue claims to read (MIPS, PowerPC, ARM, x86).

[silvervest]

Thanks, both fixed in the new last commit: a prefix (lock, rep*, xacquire/xrelease, bnd, notrack) is read with the word after it, and in a stack slot only the displacement is normalised (an index's *4/*8 and ARM's lsl #n stay). The tests run capstone's own text for x86, ARM, MIPS and PowerPC, each with a real difference and a same-but-another-slot pair.

[n-delic]

Thanks. All three points are fixed: the prefixes, _SLOT_NUMBER (scales and shift amounts), and the capstone tests for the four architectures. One small gap before merging:

ARM's shift operators aren't in _KEYWORDS (scoring.py:200-201), so the residue treats them as noise. ldr r0, [sp, r2, lsl #2] vs ldr r0, [sp, r2, asr #2] gives an empty residue, though the instructions differ. Add lsl/lsr/asr/ror/rrx (and the extend ops uxtb/uxth/sxtb/sxth/uxtw/sxtw), with a test on 02019de7 vs 42019de7.

[silvervest]

Thanks, fixed in the new last commit: ARM's shifts (lsl/lsr/asr/ror/rrx) and extends (uxtb…sxtx) are keywords, and an extend's amount in a stack slot stays like a shift's. Tests: 02019de7 vs 42019de7, plus ARM64's uxtw #2 vs sxtw #2. Both fail without the change. Rebased onto the current main.