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Incorrect multiplier in a53-pll freq_tbl#431

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Auroir:a53-pll-fix
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Incorrect multiplier in a53-pll freq_tbl#431
Auroir wants to merge 1 commit intomsm8916-mainline:wip/msm8916/6.19from
Auroir:a53-pll-fix

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@Auroir
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@Auroir Auroir commented Feb 10, 2026

Changed
1152000000 = 62 * 19200000 (xo-clock)
To
1152000000 = 60 * 19200000 (xo-clock)

Currently if you add 1152000000 (60x) to your device tree you receive a PLL of 1190400000 (62x).

Perhaps it was intended for there to be a frequency level for scenarios where a 1.2GHz limit is strictly enforced thereby disallowing 1.21GHz (63x), in which case the problem is labeling it as 1152000000 when it's 1190400000. But I think it's more likely that the intent was a smooth range of frequencies to choose from so I fixed the multiplier.

1152000000 = 60 * 19200000 (xo-clock)

Currently if you add 1152000000 (60x) to your device tree you receive a PLL of 1190400000 (62x).

Signed-off-by: Radar J’rooti <Auroir@protonmail.com>
@stephan-gh
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Looks like you're right, downstream has 60 as well:

static struct pll_freq_tbl apcs_pll_freq[] = {
	F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1152000000, 60, 0x0, 0x1, 0x0, 0x0, 0x0), // <----
	F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1363200000, 71, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
	PLL_F_END
};

Can you send this upstream to the Linux kernel mailing lists?

@Auroir
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Auroir commented Apr 25, 2026

It looks like your example has 62x as well as 60x. Should this patch instead be making entries for both?

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