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fix PLIC context interrupt mapping in Devicetree #608

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fix PLIC context interrupt mapping in Devicetree #608

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4 changes: 2 additions & 2 deletions sw/device/devicetree/mocha.S
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7 changes: 4 additions & 3 deletions sw/device/devicetree/mocha.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -79,14 +79,15 @@
};

plic: interrupt-controller@48000000 {
// Compatible with the standard and SiFive PLIC memory layout
compatible = "lowrisc,opentitan-plic",
"sifive,plic-1.0.0"; // Compatible with the SiFive PLIC memory layout
"sifive,plic-1.0.0";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x0 0x48000000 0x0 0x4000000>;
interrupts-extended = <&cpu0intc 9>, // S-mode external interrupt
<&cpu0intc 11>; // M-mode external interrupt
interrupts-extended = <&cpu0intc 11>, // Context 0: M-mode external interrupt
<&cpu0intc 9>; // Context 1: S-mode external interrupt
riscv,ndev = <32>;
};

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