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I2C SW cleanups #605
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I2C SW cleanups #605
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| Original file line number | Diff line number | Diff line change |
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@@ -26,7 +26,7 @@ uint16_t i2c_calc_scl_high_cycles(uint16_t rise_cycles, uint16_t fall_cycles, | |
| uint16_t scl_period_cycles, uint16_t scl_low_cycles, | ||
| uint16_t scl_high_cycles_min) | ||
| { | ||
| // scl_high_time should be atleast 4 cycles to aid correct clock streching | ||
| // scl_high_time should be at least 4 cycles to aid correct clock stretching | ||
| scl_high_cycles_min = (scl_high_cycles_min < 4u) ? 4u : scl_high_cycles_min; | ||
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| // An SCL period duration is divided into 4 segments: | ||
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@@ -51,8 +51,8 @@ uint16_t i2c_calc_scl_high_cycles(uint16_t rise_cycles, uint16_t fall_cycles, | |
| // specification "UM10204" Table 10 (rev. 6) / Table 11 (rev. 7). | ||
| // | ||
| // The values for Rise and Fall times for Fast mode are taken as spec minimum. For Fast plus mode, | ||
| // the values are taken from OT's i2c_host_tx_rx_test.c test. | ||
| i2c_timing_params_t compute_minimum_timing_paramaters(i2c_speed_mode_t speed) | ||
| // the values are taken from OpenTitan's i2c_host_tx_rx_test.c test. | ||
| static i2c_timing_params_t compute_minimum_timing_parameters(i2c_speed_mode_t speed) | ||
| { | ||
| switch (speed) { | ||
| case i2c_speed_mode_standard: | ||
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@@ -104,7 +104,7 @@ i2c_timing_params_t compute_minimum_timing_paramaters(i2c_speed_mode_t speed) | |
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| void i2c_init(i2c_t i2c, i2c_speed_mode_t speed_mode) | ||
| { | ||
| i2c_timing_params_t timing_params = compute_minimum_timing_paramaters(speed_mode); | ||
| i2c_timing_params_t timing_params = compute_minimum_timing_parameters(speed_mode); | ||
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| timing_params.scl_high_cycles = | ||
| i2c_calc_scl_high_cycles(timing_params.rise_cycles, timing_params.fall_cycles, | ||
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@@ -184,7 +184,7 @@ void i2c_read_bytes(i2c_t i2c, uint8_t addr, uint8_t num_bytes) | |
| VOLATILE_WRITE(i2c->fdata, fdata_reg); | ||
| } | ||
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| bool i2c_wait_write_finish(i2c_t i2c) | ||
| bool i2c_wait_transfer_finish(i2c_t i2c) | ||
| { | ||
| // Wait for transaction to complete and report simple succeed / fail | ||
| while (true) { | ||
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@@ -200,36 +200,13 @@ bool i2c_wait_write_finish(i2c_t i2c) | |
| return false; // Transaction failed | ||
| } | ||
| if (i2c_intr_state_reg & i2c_intr_cmd_complete) { | ||
| i2c_status i2c_status_reg = VOLATILE_READ(i2c->status); | ||
| if (i2c_status_reg & i2c_status_fmtempty) { | ||
| if (VOLATILE_READ(i2c->status) & i2c_status_fmtempty) { | ||
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Contributor
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I think this is probably fine as-is, just with the name
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Hmm. |
||
| return true; // Transaction succeeded | ||
| } | ||
| } | ||
| } | ||
| } | ||
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| bool i2c_wait_read_finish(i2c_t i2c) | ||
| { | ||
| // Wait for transaction to complete and report simple succeed / fail | ||
| while (true) { | ||
| i2c_intr i2c_intr_state_reg = VOLATILE_READ(i2c->intr_state); | ||
| if (i2c_intr_state_reg & i2c_intr_controller_halt) { | ||
| // Reset FMT FIFO as controller's FSM is in halt | ||
| i2c_fifo_ctrl fifo_ctrl_reg = { .fmtrst = 1u }; | ||
| VOLATILE_WRITE(i2c->fifo_ctrl, fifo_ctrl_reg); | ||
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| // According to programmer's guide, the CONTROLLER_EVENTS register would be cleared | ||
| // here to acknowledge the controller halt interrupt. However, since we want to | ||
| // treat a halt event as a failure, we intentionally skip clearing it. | ||
| return false; // Transaction failed | ||
| } | ||
| i2c_status i2c_status_reg = VOLATILE_READ(i2c->status); | ||
| if (i2c_status_reg & i2c_status_fmtempty) { | ||
| return true; | ||
| } | ||
| } | ||
| } | ||
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| void i2c_enable_controller_mode(i2c_t i2c) | ||
| { | ||
| VOLATILE_WRITE(i2c->ctrl, i2c_ctrl_enablehost); | ||
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