[hw,dv,sw] Add support for HW_ID for SW

hw/top_chip/dv/env/top_chip_dv_env_pkg.sv

@@ -41,11 +41,15 @@ package top_chip_dv_env_pkg;
   // 50 MHz Peripheral clock
   parameter int unsigned PeriClkFreq = 50_000_000;
 
-  // SW DV special write locations for test status and logging will always fit in 32-bits
+  // SW-DV special locations for test status, logging, and platform identification.
+  // These are intercepted by sim_sram_axi_sink before the AXI crossbar.
   parameter bit [31:0] SW_DV_START_ADDR       = 'h2002_0000;
   parameter bit [31:0] SW_DV_SIZE             = 'h0000_0100;        // 256 bytes reserved for SW DV
   parameter bit [31:0] SW_DV_TEST_STATUS_ADDR = SW_DV_START_ADDR + 'h00;
-  parameter bit [31:0] SW_DV_LOG_ADDR         = SW_DV_START_ADDR + 'h04;
+  parameter bit [31:0] SW_DV_HW_ID_ADDR       = SW_DV_START_ADDR + 'h04;
+  parameter bit [31:0] SW_DV_LOG_ADDR         = SW_DV_START_ADDR + 'h08;
+
+  parameter bit [31:0] SW_DV_HW_ID            = 32'h0000_002A;
 
   // File includes
   `include "mem_clear_util.sv"

hw/top_chip/dv/sim_sram_axi/sim_sram_axi_if.sv

@@ -15,6 +15,8 @@ interface sim_sram_axi_if (
   // Control signals set by the Testbench
   logic [31:0] start_addr;
   logic [31:0] sw_dv_size;
+  logic [31:0] hw_id_addr;
+  logic [31:0] hw_id;
 
   // Monitor signals driven by the Sink
   axi_req_t  req;

hw/top_chip/dv/sim_sram_axi/sim_sram_axi_sink.sv

@@ -68,6 +68,17 @@ module sim_sram_axi_sink #(
   logic [top_pkg::AxiDataWidth-1:0] mem_rdata;
   logic [top_pkg::AxiStrbWidth-1:0] mem_be;
 
+  // True when the access targets the read-only HW_ID register.
+  logic hw_id_sel;
+  assign hw_id_sel = (mem_addr[31:0] == u_sim_sram_if.hw_id_addr);
+
+  // Insert one cycle delay to align with mem_req_d
+  logic hw_id_sel_d;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) hw_id_sel_d <= 1'b0;
+    else         hw_id_sel_d <= mem_req && !mem_we && hw_id_sel;
+  end
+
   axi_to_mem #(
     .axi_req_t    (top_pkg::axi_req_t     ),
     .axi_resp_t   (top_pkg::axi_resp_t    ),
@@ -102,9 +113,9 @@ module sim_sram_axi_sink #(
     end
   end : delayed_mem_req
 
-  // Assert Error if ErrOnRead is set and a read occurs
+  // Assert Error if ErrOnRead is set and a read occurs to a non-HW_ID address.
   if (ErrOnRead) begin : gen_err_on_read
-    `ASSERT(ErrOnRead_A, mem_req |-> mem_we, clk_i, !rst_ni)
+    `ASSERT(ErrOnRead_A, (mem_req && !hw_id_sel) |-> mem_we, clk_i, !rst_ni)
   end : gen_err_on_read
 
   // Conditional SRAM Instantiation
@@ -138,9 +149,8 @@ module sim_sram_axi_sink #(
     );
   end : gen_sram
   else begin : gen_no_sram
-    // If no SRAM, return 0s on read.
-    // Handshaking is handled by the common logic and axi_to_mem.
-    assign mem_rdata = '0;
+    // If no SRAM, return hw_id for RO register reads, 0 otherwise.
+    assign mem_rdata = hw_id_sel_d ? {{(AxiDataWidth-32){1'b0}}, u_sim_sram_if.hw_id} : '0;
   end : gen_no_sram
 
   // Simulation SRAM Interface Instance

hw/top_chip/dv/tb/tb.sv

@@ -15,6 +15,8 @@ module tb;
   import top_chip_dv_env_pkg::SW_DV_START_ADDR;
   import top_chip_dv_env_pkg::SW_DV_TEST_STATUS_ADDR;
   import top_chip_dv_env_pkg::SW_DV_LOG_ADDR;
+  import top_chip_dv_env_pkg::SW_DV_HW_ID_ADDR;
+  import top_chip_dv_env_pkg::SW_DV_HW_ID;
 
   // Macro includes
   `include "uvm_macros.svh"
@@ -247,6 +249,8 @@ module tb;
     // Set base of SW DV special write locations
     `SIM_SRAM_IF.start_addr                              = SW_DV_START_ADDR;
     `SIM_SRAM_IF.sw_dv_size                              = SW_DV_SIZE;
+    `SIM_SRAM_IF.hw_id                                   = SW_DV_HW_ID;
+    `SIM_SRAM_IF.hw_id_addr                              = SW_DV_HW_ID_ADDR;
     `SIM_SRAM_IF.u_sw_test_status_if.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
     `SIM_SRAM_IF.u_sw_logger_if.sw_log_addr              = SW_DV_LOG_ADDR;
 

hw/top_chip/dv/top_chip_sim_cfg.hjson

@@ -103,6 +103,20 @@
       run_opts: ["+ChipMemSRAM_image_file={run_dir}/timer_interrupt_test_cheri_sram.vmem",
                  "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
     }
+    {
+      name: test_framework_test
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["test_framework_test_vanilla_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/test_framework_test_vanilla_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
+    {
+      name: test_framework_test_cheri
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["test_framework_test_cheri_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/test_framework_test_cheri_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
     {
       name: test_framework_exception_test
       uvm_test_seq: top_chip_dv_base_vseq
@@ -339,6 +353,8 @@
         "rv_timer_smoke_cheri",
         "rv_timer_irq",
         "rv_timer_irq_cheri",
+        "test_framework_test",
+        "test_framework_test_cheri",
         "test_framework_exception_test",
         "test_framework_exception_test_cheri",
         "spi_device_smoke",
@@ -389,6 +405,8 @@
     {
       name: test_framework
       tests: [
+        "test_framework_test",
+        "test_framework_test_cheri",
         "test_framework_exception_test",
         "test_framework_exception_test_cheri"
       ]

hw/top_chip/dv/verilator/top_chip_verilator.sv

@@ -187,9 +187,15 @@ module top_chip_verilator (
   `define DUT               u_top_chip_system
   `define SIM_SRAM_IF       u_sim_sram.u_sim_sram_if
 
+  // Special addresses for SW-DV communication
   localparam bit [31:0] VERILATOR_SW_DV_START_ADDR       = 'h2002_0000;
   localparam bit [31:0] VERILATOR_SW_DV_SIZE             = 'h0000_0100;   // 256 bytes reserved
   localparam bit [31:0] VERILATOR_SW_DV_TEST_STATUS_ADDR = VERILATOR_SW_DV_START_ADDR + 'h00;
+  localparam bit [31:0] VERILATOR_SW_DV_HW_ID_ADDR       = VERILATOR_SW_DV_START_ADDR + 'h04;
+
+  // Specific ID for SW-DV to identify that it's running on Verilator. This can be used by
+  // SW to adapt its behavior when running on Verilator vs other simulators or real hardware.
+  localparam bit [31:0] VERILATOR_HW_ID                  = 32'h0000_001A;
 
   // Signals to connect the sink
   top_pkg::axi_req_t  sim_sram_cpu_req;
@@ -228,10 +234,12 @@ module top_chip_verilator (
     .data     (`SIM_SRAM_IF.req.w.data[15:0] )  // Test status is 16-bits wide
   );
 
-  // Set the start address and the size of the simulation SRAM
+  // Set special SW-DV registers
   initial begin
     `SIM_SRAM_IF.start_addr                 = VERILATOR_SW_DV_START_ADDR;
     `SIM_SRAM_IF.sw_dv_size                 = VERILATOR_SW_DV_SIZE;
+    `SIM_SRAM_IF.hw_id_addr                 = VERILATOR_SW_DV_HW_ID_ADDR;
+    `SIM_SRAM_IF.hw_id                      = VERILATOR_HW_ID;
     u_sw_test_status_if.sw_test_status_addr = VERILATOR_SW_DV_TEST_STATUS_ADDR;
   end
 

hw/top_chip/rtl/chip_mocha_genesys2.sv

@@ -76,6 +76,7 @@ module chip_mocha_genesys2 #(
 );
   // Local parameters
   localparam int unsigned InitialResetCycles = 4;
+  localparam bit [31:0]   FpgaHwId           = 32'h0000_000A;   // FpgaGenesys2
 
   // Rest of chip AXI crossbar configuration
   localparam axi_pkg::xbar_cfg_t xbar_cfg = '{
@@ -97,7 +98,8 @@ module chip_mocha_genesys2 #(
   // Rest of chip AXI crossbar address mapping
   axi_pkg::xbar_rule_64_t [xbar_cfg.NoAddrRules-1:0] addr_map;
   assign addr_map = '{
-    '{ idx: top_pkg::Ethernet, start_addr: top_pkg::EthernetBase, end_addr: top_pkg::EthernetBase + top_pkg::EthernetLength }
+    '{ idx: top_pkg::SwDvWindowDevIdx, start_addr: top_pkg::SwDvWindowBase, end_addr: top_pkg::SwDvWindowBase + top_pkg::SwDvWindowLength },
+    '{ idx: top_pkg::Ethernet,         start_addr: top_pkg::EthernetBase,   end_addr: top_pkg::EthernetBase   + top_pkg::EthernetLength   }
   };
 
   // Internal clock signals
@@ -155,6 +157,14 @@ module chip_mocha_genesys2 #(
   // Ethernet interrupt line
   logic ethernet_irq;
 
+  // SW-DV window AXI subordinate memory interface acting as a sink
+  logic                             hw_id_mem_req;
+  logic                             hw_id_mem_req_q;
+  logic                             hw_id_mem_we;
+  logic [top_pkg::AxiAddrWidth-1:0] hw_id_mem_addr;
+  logic [top_pkg::AxiDataWidth-1:0] hw_id_mem_rdata;
+  logic                             hw_id_sel_q;
+
   // Clock generation
   clkgen_xil7series u_clk_gen (
     .clk_200m_i      (clk_200m),
@@ -562,4 +572,44 @@ module chip_mocha_genesys2 #(
     .eth_rgmii_mdc_o    (eth_mdc)
   );
 
+  // SW-DV window: read-only HW_ID register.
+  // Uses the same axi_to_mem + 1-cycle loopback pattern as sim_sram_axi_sink.
+  // Writes are accepted and discarded. Reads return FpgaHwId at offset +0x08, 0 elsewhere.
+  axi_to_mem #(
+    .axi_req_t    (top_pkg::axi_req_t   ),
+    .axi_resp_t   (top_pkg::axi_resp_t  ),
+    .DataWidth    (top_pkg::AxiDataWidth),
+    .AddrWidth    (top_pkg::AxiAddrWidth),
+    .IdWidth      (top_pkg::AxiIdWidth  ),
+    .NumBanks     (1                    )
+  ) u_hw_id_axi_to_mem (
+    .clk_i        (u_top_chip_system.clkmgr_clocks.clk_main_infra                       ),
+    .rst_ni       (u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]),
+    .busy_o       (                                                                     ),
+    .axi_req_i    (xbar_device_req [top_pkg::SwDvWindowDevIdx]                          ),
+    .axi_resp_o   (xbar_device_resp[top_pkg::SwDvWindowDevIdx]                          ),
+    .mem_req_o    (hw_id_mem_req                                                        ),
+    .mem_gnt_i    (1'b1                                                                 ),
+    .mem_addr_o   (hw_id_mem_addr                                                       ),
+    .mem_wdata_o  (                                                                     ),  // Ignored: RO register
+    .mem_strb_o   (                                                                     ),  // Ignored: RO register
+    .mem_atop_o   (                                                                     ),  // Not used
+    .mem_we_o     (hw_id_mem_we                                                         ),
+    .mem_rvalid_i (hw_id_mem_req_q                                                      ),
+    .mem_rdata_i  (hw_id_mem_rdata                                                      )
+  );
+
+  always_ff @(posedge u_top_chip_system.clkmgr_clocks.clk_main_infra
+              or negedge u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]) begin
+    if (!u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]) begin
+      hw_id_mem_req_q <= 1'b0;
+      hw_id_sel_q     <= 1'b0;
+    end else begin
+      hw_id_mem_req_q <= hw_id_mem_req;
+      hw_id_sel_q     <= hw_id_mem_req && !hw_id_mem_we && (hw_id_mem_addr[7:0] == 8'h04);
+    end
+  end
+
+  assign hw_id_mem_rdata = hw_id_sel_q ? {{(top_pkg::AxiDataWidth-32){1'b0}}, FpgaHwId} : '0;
+
 endmodule

hw/top_chip/rtl/top_pkg.sv

@@ -40,7 +40,7 @@ package top_pkg;
     SRAMBase       = 64'h1000_0000,
     DebugMemBase   = 64'h2000_0000,
     MailboxBase    = 64'h2001_0000,
-    RestOfChipBase = 64'h3000_0000,
+    RestOfChipBase = 64'h2002_0000,
     TlCrossbarBase = 64'h4000_0000,
     DRAMBase       = 64'h8000_0000
   } axi_addr_start_t;
@@ -50,7 +50,7 @@ package top_pkg;
   localparam longint unsigned SRAMLength         = 64'h0002_0000;
   localparam longint unsigned DebugMemLength     = 64'h0000_1000;
   localparam longint unsigned MailboxLength      = 64'h0001_0000;
-  localparam longint unsigned RestOfChipLength   = 64'h0000_8000;
+  localparam longint unsigned RestOfChipLength   = 64'h0FFE_8000;   // 0x2002_0000 to 0x3000_7FFF
   localparam longint unsigned TlCrossbarLength   = 64'h1000_0000;
   localparam longint unsigned DRAMPhysicalLength = 64'h4000_0000;
 
@@ -64,23 +64,26 @@ package top_pkg;
 
   // Rest of chip AXI crossbar parameters
   localparam int RestOfChipAxiXbarHosts   = 1;
-  localparam int RestOfChipAxiXbarDevices = 1;
+  localparam int RestOfChipAxiXbarDevices = 2;
 
   // Rest of chip AXI crossbar hosts and devices
   typedef enum int unsigned {
     MochaAXICrossbar = 0
   } rest_of_chip_axi_hosts_t;
 
   typedef enum int unsigned {
-    Ethernet = 0
+    Ethernet         = 0,
+    SwDvWindowDevIdx = 1
   } rest_of_chip_axi_devices_t;
 
   typedef enum longint unsigned {
-    EthernetBase = 64'h3000_0000
+    EthernetBase   = 64'h3000_0000,
+    SwDvWindowBase = 64'h2002_0000
   } rest_of_chip_axi_addr_start_t;
 
   // Memory lengths
-  localparam longint unsigned EthernetLength = 64'h0000_8000;
+  localparam longint unsigned EthernetLength   = 64'h0000_8000;
+  localparam longint unsigned SwDvWindowLength = 64'h0000_0100;
 
   // Memory address masks
   localparam longint unsigned EthernetMask = EthernetLength - 1;

sw/device/lib/hal/dv.h

@@ -0,0 +1,47 @@
+// Copyright lowRISC contributors (COSMIC project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Design Verification (DV) register window.
+
+#pragma once
+
+#include <stdint.h>
+
+/* These values are written to the test_status register of the DV window
+ * throughout a test to indicate test progression and outcome. */
+enum dv_test_status : uint32_t {
+    /* Test code has begun. */
+    dv_test_status_in_test = 0x4354u,
+    /* The test has passed. */
+    dv_test_status_passed = 0x900du,
+    /* The test has failed. */
+    dv_test_status_failed = 0xbaadu,
+};
+
+/* These values are provided by the DV window from the hw_id register to
+ * indicate the current test platform. */
+enum dv_hwid : uint32_t {
+    /* Running on the Genesys2 FPGA. */
+    dv_hwid_fpga_genesys2 = 0xau,
+    /* Running in a Verilator simulation. */
+    dv_hwid_sim_verilator = 0x1au,
+    /* Running in a UVM simulation. */
+    dv_hwid_sim_uvm = 0x2au,
+};
+
+typedef volatile struct [[gnu::aligned(4)]] dv_window_memory_layout {
+    /* test_status (0x0) */
+    uint32_t test_status;
+
+    /* hw_id (0x4) */
+    const uint32_t hw_id;
+
+    const uint8_t __reserved0[0x100 - 0x08];
+} *dv_window_t;
+
+
+_Static_assert(__builtin_offsetof(struct dv_window_memory_layout, test_status) == 0x0ul,
+               "incorrect register test_status offset");
+_Static_assert(__builtin_offsetof(struct dv_window_memory_layout, hw_id) == 0x4ul,
+               "incorrect register hw_id offset");

sw/device/lib/hal/mocha.c

@@ -13,7 +13,7 @@
 
 static const uintptr_t rom_base = 0x80000ul;
 static const uintptr_t mailbox_base = 0x20010000ul;
-static const uintptr_t dv_test_status_base = 0x20020000ul;
+static const uintptr_t dv_window_base = 0x20020000ul;
 static const uintptr_t ethernet_base = 0x30000000ul;
 static const uintptr_t gpio_base = 0x40000000ul;
 static const uintptr_t clkmgr_base = 0x40020000ul;
@@ -193,11 +193,12 @@ void *mocha_system_dram(void)
 #endif /* defined(__riscv_zcherihybrid) */
 }
 
-void *mocha_system_dv_test_status(void)
+dv_window_t mocha_system_dv_window(void)
 {
 #if defined(__riscv_zcherihybrid)
-    return create_mmio_capability(dv_test_status_base, 0x100u);
+    return (
+        dv_window_t)create_mmio_capability(dv_window_base, sizeof(struct dv_window_memory_layout));
 #else /* !defined(__riscv_zcherihybrid) */
-    return (void *)dv_test_status_base;
+    return (dv_window_t)dv_window_base;
 #endif /* defined(__riscv_zcherihybrid) */
 }

sw/device/lib/hal/mocha.h

@@ -7,6 +7,7 @@
 #pragma once
 
 #include "hal/clkmgr.h"
+#include "hal/dv.h"
 #include "hal/entropy_src.h"
 #include "hal/ethernet.h"
 #include "hal/gpio.h"
@@ -50,5 +51,4 @@ timer_t mocha_system_timer(void);
 spi_host_t mocha_system_spi_host(void);
 plic_t mocha_system_plic(void);
 void *mocha_system_dram(void);
-
-void *mocha_system_dv_test_status(void);
+dv_window_t mocha_system_dv_window(void);