[ImportVerilog] Add basic event type support

[fabianschuiki]

Add rudimentary support for the event type to ImportVerilog by treating events as i1 signals, where an event is signaled by inverting the value of the signal. There are likely more subtleties here that we will need to handle in the future. This covers some of the basics, though.

Error diff on circt-tests:

-36 error: unsupported type: EventType
 +6 error: unsupported non-blocking assignment timing control: SignalEvent
 +3 error: failed to legalize operation 'moore.global_variable'
 +3 error: unsupported expression: NewArray
 +2 error: failed to legalize operation 'moore.fmt.time'
 +2 error: failed to legalize operation 'moore.time_to_logic'
 +2 error: unknown hierarchical name `toplevel_event`
 +1 error: 'llhd.wait' op expects parent op 'llhd.process'
 +1 error: 'moore.read' op using value defined outside the region
 +1 error: unsupported non-blocking assignment timing control: EventList
 +1 error: unsupported repeated event control
 +1 error: unsupported statement: Disable
-13 total change