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[debug][firrtl] Carry Chisel source-level types through the pipeline#10410

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[debug][firrtl] Carry Chisel source-level types through the pipeline#10410
fkhaidari wants to merge 1 commit into
llvm:mainfrom
fkhaidari:fk-sc/debug-info

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@fkhaidari fkhaidari commented May 7, 2026

Hi! This commit carry Chisel source-level type information (type names, enum definitions, constructor parameters) through the FIRRTL -> MLIR pipeline so downstream consumers (Tywaves, HGDB) can recover the original Chisel types

Based on @rameloni's prior Tywaves/CIRCT debug-info work (#6983, #7246, chipsalliance/chisel#4224, chipsalliance/chisel#4015), but uses intrinsics instead of annotations. This PR pairs with the frontend intrinsics from chipsalliance/chisel#5276

The dbg dialect extensions (dbg.enumdef, dbg.subfield, dbg.moduleinfo) are language-agnostic and reusable by any frontend; the FIRRTL side adds handlers in firrtl-lower-intrinsics for the new circt_debug_{var,subfield,enumdef,moduleinfo} intrinsics that feed them

I am also working on a new debug output format (UHDI) -- it is intended to avoid changes to the current HGLDD format and to let existing HGL debug tools (Tywaves, HGDB, ChiselTrace, etc.) work without maintaining outdated forks. Work is still in progress (demo repo: https://github.com/fkhaidari/uhdi, CIRCT UHDI PR: fkhaidari#2).

Extends the `dbg` dialect and `firrtl-lower-intrinsics` to propagate
Chisel type names, enum definitions, and constructor parameters into
MLIR so downstream consumers (Tywaves, HGDB) can access them.

- New `dbg` ops: `dbg.enumdef`, `dbg.subfield`, `dbg.moduleinfo`.
  `dbg.variable` gets optional `typeName` / `params` / `enumDef`.
- Frontend intrinsics `circt_debug_{var,subfield,enumdef,moduleinfo}`
  are lowered in two phases: a pre-scan collects enumdefs and leaf
  metadata into `DebugIntrinsicPreScan`, then `CirctDebugVarConverter`
  walks each aggregate into `dbg.struct` / `dbg.array`, wrapping every
  leaf and intermediate aggregate in `dbg.subfield` with its typeName.
- Non-passive root aggregates are emitted with 0 SSA operands;
  the converter looks up the matching port/wire by name.
- `MaterializeDebugInfo` skips names already covered by `circt_debug_var`
  to avoid duplicate `dbg.variable`.
- Tests in `test/Dialect/Debug/` and `test/Dialect/FIRRTL/lower-intrinsics-debug.mlir`.

Signed-off-by: fkhaidari <khaidari.fg@gmail.com>
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