[PW_SID:1068597] PolarFire SoC GPIO interrupt support#1636
[PW_SID:1068597] PolarFire SoC GPIO interrupt support#1636linux-riscv-bot wants to merge 5 commits intoworkflow__riscv__fixesfrom
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The microchip,mpfs-gpio binding suffered greatly due to being written with a narrow minded view of the controller, and the interrupt bits ended up incorrect. It was mistakenly assumed that the interrupt configuration was set by platform firmware, based on the FPGA configuration, and that the GPIO DT nodes were the only way to really communicate interrupt configuration to software. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, try to fix the misconceptions in the GPIO controller binding. Firstly, it's not possible for this controller to have fewer than 14 GPIOs, and thus 14 interrupts also. There are three controllers, with 14, 24 & 32 GPIOs each. The fabric core, CoreGPIO, can of course have a customisable number of GPIOs. The example is wacky too - it follows from the incorrect understanding that the GPIO controllers are connected to the PLIC directly. They are not however, with a mux sitting in between. Update the example to use the mux as a parent, and the interrupt numbers at the mux for GPIO2 as the example - rather than the strange looking, repeated <53>. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add support for interrupts to the PolarFire SoC GPIO driver. Each GPIO has an independent interrupt that is wired to an interrupt mux that sits between the controllers and the PLIC. The SoC has more GPIO lines than connections from the mux to the PLIC, so some GPIOs must share PLIC interrupts. The configuration is not static and is set at runtime, conventionally by the platform's firmware. CoreGPIO, the version intended for use in the FPGA fabric has two interrupt output ports, one is IO_NUM bits wide, as is used in the hardened cores, and the other is a single bit with all lines ORed together. Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Reviewed-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Add a driver so that Linux can set the mux based on the interrupt mapping in the devicetree. Reviewed-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…e SoC There are 3 GPIO controllers on this SoC, of which: - GPIO controller 0 has 14 GPIOs - GPIO controller 1 has 24 GPIOs - GPIO controller 2 has 32 GPIOs All GPIOs are capable of generating interrupts, for a total of 70. There are only 41 IRQs available however, so a configurable mux is used to ensure all GPIOs can be used for interrupt generation. 38 of the 41 interrupts are in what the documentation calls "direct mode", as they provide an exclusive connection from a GPIO to the PLIC. The 3 remaining interrupts are used to mux the interrupts which do not have a exclusive connection, one for each GPIO controller. The mux was overlooked when the bindings and driver were originally written for the GPIO controllers on Polarfire SoC, and the interrupts property in the GPIO nodes used to try and convey what the mapping was. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, fix the inaccurate description of the interrupt controller hierarchy. GPIO controllers 0 and 1 do not have all 32 possible GPIO lines, so ngpios needs to be set to match the number of lines/interrupts. The m100pfsevp has conflicting interrupt mappings for controllers 0 and 2, as they cannot both be using an interrupt in "direct mode" at the same time, so the default replaces this impossible configuration. Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 1: "[v13,1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 2: "[v13,2/5] gpio: mpfs: Add interrupt support" |
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Patch 3: "[v13,3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux" |
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Patch 3: "[v13,3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux" |
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Patch 3: "[v13,3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux" |
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Patch 3: "[v13,3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux" |
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Patch 3: "[v13,3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 4: "[v13,4/5] soc: microchip: add mpfs gpio interrupt mux driver" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
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Patch 5: "[v13,5/5] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC" |
PR for series 1068597 applied to workflow__riscv__fixes
Name: PolarFire SoC GPIO interrupt support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1068597
Version: 13