[PW_SID:1067129] riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC#1618
[PW_SID:1067129] riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC#1618linux-riscv-bot wants to merge 3 commits intoworkflow__riscv__fixesfrom
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Previously only auipc+jalr pair is supported. Add auipc+load pair to support PC-relative memory load instruction as well. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Enhance the errata/sifive patching function to support auipc/load insn pair by fixing the offsets in immediate, just like in function `riscv_cpufeature_patch_func`. Refer to commit 27c653c ("RISC-V: fix auipc-jalr addresses in patched alternatives") Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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On some platforms with pre-Svpbmt Sifive cores, they map the system
memory twice in physical address space, one as cached (through the
front port), and the other as uncached (through the system port), to
enable drivers working with non-cache-coherent devices. Drivers can map
the DMA buffers uncached through the uncached alias, and don't have to
flush caches explicitly. It eases the driver programming. For complex
device drivers, such as the GPU, this is a must have, as DMA pages can
be mmap'ed to user space, and the userspace can't do caches flushes due
to the lack of Zicbom on these older cores.
Introduce a Sifive "errata" to model such setup with a customized
version of Svpbmt, "XPbmtUC", where a single, artificial bit in the PTE
is used for cache/uncache control (UC), effectively offsetting the PPN
by power-of-2. I.e.,
Starfive JH7110 (Sifive U74):
[0x0, 0x40000000) Low MMIO
[0x40000000, 0x2_40000000) Cached Mem
[0x4_40000000, 0x6_40000000) Uncached Mem UC+
[0x9_00000000, 0x9_d0000000) High MMIO
Using PTE bit 32 (PPN bit 34) as UC (uncache) control perfectly matches
the memory map of the SoC.
Other SoCs like ESWIN EIC770X is not directly compatible to this model,
as the uncached regions are not power-of-2 offseted, and the offsets are
different between Dies in the dual-die version (EIC7702). The firmware,
however, could use G-stage page table to transparently re-map, and make
the address space suitable for XPbmtUC scheme to be applied:
[0x0, 0x20000000) Core Internal
[0x20000000, 0x40000000) Core Internal (Die 1)
[0x40000000, 0x60000000) Low MMIO
[0x60000000, 0x80000000) Low MMIO (Die 1)
[0x80000000, 0x10_80000000) Cached Mem
[0x20_00000000, 0x30_00000000) Cached Mem (Die 1)
[0x80_00000000, 0xa0_00000000) High MMIO
[0xa0_00000000, 0xc0_00000000) High MMIO (Die 1)
[0xc0_00000000, 0xd0_00000000) Uncached Mem <----------.
[0xe0_00000000, 0xf0_00000000) Uncached Mem (Die 1) <--+--.
with firmware/hypervisor re-mapping: | |
------------------------------------ | |
[0x100_80000000, 0x110_80000000) Mem UC+ ----------------' |
[0x120_00000000, 0x130_00000000) Mem UC+ (Die 1) -----------'
Such firmware capability is detected at boot time by sbi ecalls. The
firmware will provide us the UC bit position if re-map is in effect.
Note: currently this feature is gated by JH7110 and EIC770X SoCs to
avoid unnecessary sbi ecalls. There's also no IO bit in such XPbmtUC
scheme, as it's assumed that the PMA (hard-wired on these SoCs) will
convey the strongly-ordered, non-idempotent attribute of MMIO regions.
Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 1: "[RFC,v2,1/3] riscv: alternatives: support auipc+load pair" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 2: "[RFC,v2,2/3] riscv: errata: sifive: support auipc/load pair in patched alternatives" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
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Patch 3: "[RFC,v2,3/3] riscv: errata: sifive: Add an "errata" to simulate Svpbmt on cores without" |
2 participants
PR for series 1067129 applied to workflow__riscv__fixes
Name: riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1067129
Version: 2