Perf: skip the empty Tier-0 staging order in the a5 dispatch loop

[lwDavid]

dispatch_ready_tasks runs run_staging_order twice per iteration:
once over ready_sync_queues (Tier-0) and once over ready_queues.
Each pass probes up to six shape/phase combinations, so the loop pays
twelve queue probes per iteration whatever is actually queued.
Scheduler profiling agrees: thread 0 reported 1419 pop atomics against
113 loop iterations, i.e. 12.6 per iteration.

Only a task with requires_sync_start() can ever reach Tier-0, so a
program without one leaves those six probes reading empty queues for
its entire run. This adds a latch, sync_task_seen, and skips the
Tier-0 staging order while it is clear.

Where the latch is armed, and what it does and does not guarantee

The latch is set in prepare_task(), at SUBMIT — not on the
ready-queue push, so arming cannot depend on what
ChipReadyQueue::push returns (it reports false on a full queue).

It does NOT make the latch instantaneous. A thread can read it clear,
the arming store can land, the push can land, and that thread can
still spend the rest of its iteration in Tier-1. The accurate
statement is that Tier-0 priority is best-effort for an entry that
becomes visible mid-iteration: a thread already past its Tier-0
checkpoint picks it up on its next pass, whether that checkpoint is
this latch load or the six queue probes it stands in for. The latch
load happens no later than the first of those probes would have.

The store is release and the dispatch-loop load is acquire, so
observing the latch set also makes that task's submission visible.
sync_task_seen sits on its own cache line — written once per epoch,
read once per dispatch iteration. Programs that DO use sync_start are
unaffected: the latch stays set for the rest of the epoch and Tier-0
runs unconditionally.

Measurement, with a placebo control

DSv4-Pro decode attention on a5, interleaved A/B with a runtime
rebuild per arm, 100 rounds per arm, golden PASS on every completed
variant arm.

Because the effect is small and the HCA baseline spreads about 2.4%
run to run, the harness was first checked against itself: a placebo
arm whose only difference from base is one added comment line.

arm	delta	reps won by "variant"
placebo, 3 reps	-0.55%	2 of 3
placebo, 5 reps	-0.18%	3 of 5

At five reps the placebo is indistinguishable from zero and its
per-rep split is a coin flip, so the harness has no meaningful
directional bias toward the second arm. Note the three-rep placebo
landed at -0.55% with a 2-of-3 split — a three-rep result of that size
is not separable from noise, which is why HCA was given five.

Against that control, the real change:

kernel	observed range	reps
SWA	-1.0% to -2.3%	3, 3, 2
CSA	-0.6% to -1.6%	3, 3
HCA	-1.7% to -2.0%	3, 5

Every one of those runs won every completed rep, which the placebo
does not. The honest reading is a real effect of roughly 1-2%, not
a settled per-kernel figure.

One caveat for anyone stacking this with other decode work: measured
together with a separate pypto-lib change, the two do not sum on HCA.
Both appear to attack the same scheduler-idle slack, so quote a
stacked measurement rather than adding separate ones.

A note for anyone comparing DFX data across versions

Skipping Tier-0 removes six empty probes per iteration from pop_miss
and g_sched_pop_atomic_count. The 12.6 pops/iteration quoted above
is a pre-change number; after this, a non-sync_start program reads
about half that. The documented meaning of those counters does not
change, but the denominator does.

Scope

Four files, +46/-13, in a5/tensormap_and_ringbuffer only.
a2a3/tensormap_and_ringbuffer and both host_build_graph runtimes
carry the same two-tier staging structure and could take the same
latch — a2a3/tmr in particular has a matching prepare_task and a
verbatim-corresponding insertion point. They are left for a follow-up
for one reason only: only a5 hardware was available to measure on,
and this is a performance change that should not ship to a platform it
has not been measured on.

No behaviour change for sync_start programs and no change to the
ready-dispatch policy itself.

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📝 Walkthrough

Walkthrough

The scheduler now counts routed sync_start tasks, skips sync queue probing when the count is zero, and resets the count during scheduler reuse.

Changes

Sync Queue Tracking

Layer / File(s)	Summary
Sync push accounting src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler.h	Adds cache-line-isolated atomic sync_push_count state. Profiling and non-profiling readiness paths increment it before enqueueing sync_start tasks.
Guarded dispatch and reuse reset src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp, src/a5/runtime/tensormap_and_ringbuffer/runtime/shared/runtime_init.cpp	Guards sync-start queue staging with a relaxed counter load. Resets the counter during scheduler reuse after clearing the corresponding queue.

Estimated code review effort: 2 (Simple) | ~10 minutes

Merge Risk: 🟡 Moderate · up to ef9f9

The scheduler optimization can reduce intended performance gains after a failed sync-queue insertion and may allow regular work to be staged ahead of available sync-start work. The Tier-0 priority publication gap should be resolved before merging.

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The patch grows clear beneath the moon,
Small changes hop in place,
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Reviews bloom before the dawn.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 33.33% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 3 functions across 3 files.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Title check	✅ Passed	The title clearly and concisely describes the main performance change: skipping empty Tier-0 staging in the a5 dispatch loop.
Description check	✅ Passed	The description directly explains the scheduler optimization, latch behavior, scope, measurements, and expected impact. It is fully related to the changeset.

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Inline comments:
In
`@src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp`:
- Line 535: Update dispatch_ready_tasks() so a non-empty ready_sync_queues[]
always preserves strict Tier-0 priority, even when sync_push_count reads zero;
use an appropriate queue-state check or synchronization that atomically or
reliably observes the queue publication before allowing Tier 1 regular work to
publish.

In `@src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler.h`:
- Line 576: Update all three routing paths around ChipReadyQueue::push so
sync_push_count is incremented only after push returns true. Preserve the
existing queue insertion behavior and ensure failed insertions do not set the
latch or leave sync_push_count nonzero.

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📥 Commits

Reviewing files that changed from the base of the PR and between 5cb790c and ef9f9bb.

📒 Files selected for processing (3)

• src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler.h
• src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp
• src/a5/runtime/tensormap_and_ringbuffer/runtime/shared/runtime_init.cpp

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