Feature: add dispatch-correlated same-host multi-rank swimlane timeline - #2099
Feature: add dispatch-correlated same-host multi-rank swimlane timeline#2099doraemonmj wants to merge 1 commit into
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📝 WalkthroughWalkthroughThe change adds same-host L3 multi-Rank swimlane capture and merging. It adds dispatch identity metadata, Host/Device clock anchors, Rank-scoped diagnostic outputs, directory conversion, validation, and related documentation and tests. ChangesL3 multi-Rank swimlane
Estimated code review effort: 4 (Complex) | ~60 minutes Merge Risk: 🟡 Moderate · up to The new multi-rank trace conversion currently fails on supported Python 3.9 environments, and the shared runtime mailbox change lacks a demonstrated mixed-version or rollback contract. Merge should wait for the runtime compatibility fix and explicit deployment handling; mutable local capture metadata is an additional bounded trace-integrity concern. Sequence Diagram(s)sequenceDiagram
participant ChipWorker
participant SceneTest
participant SwimlaneConverter
participant PerfettoTrace
ChipWorker->>SceneTest: write rankN/dN captures and dispatch_identity.json
SceneTest->>SwimlaneConverter: select dispatch or dispatch identity
SwimlaneConverter->>SwimlaneConverter: validate Rank captures and shared clock domain
SwimlaneConverter->>PerfettoTrace: emit namespaced cross-Rank trace
Poem
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Linked Issues checkExplanation The changes satisfy issue Full details: Out of Scope Changes checkExplanation The changes are within scope for issue Full details: Docstring CoverageExplanation Docstring coverage is 21.67% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 120 functions across 25 files. (7 skipped: 6 unsupported, 1 too large.)
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Inline comments:
In `@docs/dfx/chip-swimlane-profiling.md`:
- Around line 435-436: Update the output-path guidance in the profiling
documentation to distinguish file-input and directory-input defaults: retain
outputs/<case>_<ts>/merged_swimlane.json for file input and state
dfx_outputs/l3_swimlane.json for directory input, while preserving the -o
override guidance.
In `@simpler_setup/tools/README.md`:
- Around line 160-166: Update the Command-Line Options table to document the
--dispatch and --dispatch-id selectors, and clarify that the input argument
accepts a dfx_outputs directory when operating in directory mode.
In `@simpler_setup/tools/swimlane_converter.py`:
- Around line 3206-3209: Update the group_discovered construction to remove the
Python 3.10-only strict=True argument from zip(). Preserve the existing parallel
pairing behavior, relying on the established invariant that discovered and
identities are built together and have matching lengths.
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📒 Files selected for processing (32)
.gitignoreconftest.pydocs/dfx/chip-swimlane-profiling.mddocs/dfx/hbg-bind-phases.mddocs/task-flow.mddocs/user/reference/python-api.mdpython/bindings/task_interface.cpppython/simpler/worker.pysimpler_setup/scene_test.pysimpler_setup/tools/README.mdsimpler_setup/tools/clock_correlation.pysimpler_setup/tools/swimlane_converter.pysrc/a2a3/platform/sim/host/device_runner.cppsrc/a5/platform/sim/host/device_runner.cppsrc/common/hierarchical/remote_wire.cppsrc/common/hierarchical/worker_manager.cppsrc/common/hierarchical/worker_manager.hsrc/common/platform/include/host/clock_correlation.hsrc/common/platform/onboard/host/device_runner_base.cppsrc/common/platform/onboard/host/device_runner_base.hsrc/common/platform/shared/host/chip_swimlane_collector.cppsrc/common/platform/sim/host/device_runner_base.cppsrc/common/platform/sim/host/device_runner_base.hsrc/common/task_interface/call_config.htests/ut/cpp/hierarchical/test_scheduler.cpptests/ut/cpp/types/test_call_config.cpptests/ut/py/test_chip_worker.pytests/ut/py/test_clock_correlation.pytests/ut/py/test_scene_level_selection.pytests/ut/py/test_scene_test_cli_contract.pytests/ut/py/test_swimlane_converter.pytests/ut/py/test_worker/test_host_worker.py
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Capture and merge same-host multi-rank Chip Swimlane data on one timeline. Carry the parent run, task-slot, and group identity through the L3 mailbox so rank-local captures can be paired by stable dispatch identity instead of coincidental local dN indexes. Request the Host/Device clock anchors through CallConfig.capture_clock_anchors so the runtime enables them from an explicit field rather than by parsing the output directory. The field names what the runtime does, never who consumes it: Rank, group and merge stay concepts of the layer above, so the platform runner that reads it has no notion of a Rank and no runtime or platform code parses the rankN/dN path. The two runtimes open that interval at different points — before Host orchestration for host_build_graph, before kernel launch for tensormap_and_ringbuffer — because each takes it at the earliest point preceding its own device timestamps; the serialized position name predates the second case and is documented rather than renamed, being an on-wire value in every existing capture. Separate one ChipWorker child's artifacts from its siblings' for every diagnostic that writes below output_prefix, not the swimlane alone. Those filenames are fixed, so N children sharing one prefix overwrite each other. The clock anchors stay swimlane-only, because only that reader places its records against a Host timeline. A failure to write that per-dispatch directory is reported as the task's own error, so a full or read-only output_prefix cannot leave the mailbox loop without publishing TASK_DONE and strand the parent on a run that never completes. Offline discovery of chip_swimlane_records.json searches recursively, since an L3 capture now sits two levels deeper than an L2 one. Forward the parent's case, diagnostic and round selection to the resource child that runs an L3 case. That child's argv is built from scratch so it can be narrowed to one nodeid, so an option absent from it never reaches the case at all: an L3 chip-swimlane run passed while writing no artifact. The gap predates this change and was unreachable while L3 rejected the flag outright, and it is invisible to a green pipeline because a dropped diagnostic changes no assertion. A nodeid names a whole SceneTestCase class and --case filters inside its single test_run item at run time, so a child without the selector runs every case of the class the parent narrowed to one. Validate group membership, Rank uniqueness, callable identity, and sidecar/path agreement during conversion. Retain explicit local-dN fallback for legacy and individual submissions, add dispatch-id selection, and reject a view pid too wide for the per-Rank namespace stride. Discovery keeps each capture's identity in the same record as its path rather than in a parallel list, which also holds the tool to the Python 3.9 floor the project declares. A remainder that cannot be paired by dN downgrades to a warning instead of discarding the parent-identity targets, which pair by run and task slot and are unaffected by it. Convert each rankN/dN capture on its own relative timeline when a capture is known to be below level 4, since cross-Rank merging needs the Host/Device clock anchors that only level 4 collects. Update SceneTest postprocessing, and cover the mailbox, identity, converter, child-argv, and worker paths.
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Closes #2058
Summary
Merge every Rank's L2 chip swimlane into one Perfetto-loadable trace on a common
Host timeline.
Per-Rank captures cannot simply be concatenated: each die's cycle domain has its
own base. On a 4-card run measured here the raw offset between two Ranks was
11.56 s while the real start skew was 1.60 ms — a naive merge produces a
plausible-looking, wrong trace. The converter therefore maps each Rank's cycles
to Host
CLOCK_MONOTONICthrough that Rank's own clock anchors before merging,and refuses to merge at all when a Rank is uncalibrated or comes from a
different Host clock domain.
What changed
swimlane_converter. Directory input plus--dispatch dNor--dispatch-id RUN_ID:TASK_SLOT; per-Rank PID/name/flownamespaces; alignment method and uncertainty recorded in trace metadata.
task_slot,group_indexandgroup_sizenow travel with a task frame, so Ranks pair bystable parent-DAG identity instead of coincidental local
dNordering, whichpipelining and prepare-only frames can reorder.
CallConfig.capture_clock_anchors. The runtime learns from an explicitfield that it must anchor both clocks, rather than by parsing the output
directory. Device/AICPU orchestration had no anchors at all before this.
output_prefixnow lands inrankN/dN/— the filenames are fixed, so NChipWorker children sharing one prefix used to overwrite each other. The clock
anchors stay swimlane-only, so a dep_gen-only L3 run gets the directory
separation without paying for the anchors.
conftestbuilds that child's argv from scratch, so
--enable-chip-swimlaneand theother diagnostic options never reached an L3 case: the run passed and wrote no
artifact. The gap predates this PR and was unreachable while L3 rejected the
flag outright, and it is invisible to a green pipeline because a dropped
diagnostic changes no assertion. Without this, the feature does not work under
pytest — which is how CI runs.
Why no
--align=none#2058 allows an escape hatch that merges raw, unaligned cycle values. This PR
refuses instead — an unaligned merge is exactly the "plausible-looking, wrong
trace" the issue opens with (7.2 s of fake skew across 1–62 ms capture windows),
and a Chrome-trace file cannot tell the viewer that its lanes are incomparable:
the rendering asserts "left is earlier" on its own. Nothing is lost — single-file
per-Rank conversion is unchanged, and SceneTest falls back to it below level 4.
Two costs, accepted rather than hidden: captures predating this PR carry no
host_clock_domain_idand stay single-file only, and one Rank with failedanchors fails the whole merge rather than merging the calibrated remainder.
Verification
ut-py2108 passed,ut-cpp128/128, ruff / clang-format / retired-names clean.--enable-chip-swimlane 4: all four Rankscalibrated, paired by
parent_dispatch_identity,trace_status: complete.Kernel durations spanned 16.2 µs to 10.60 ms, yet all four lanes ended within
12.7 µs of each other against a 58.1 µs cross-Rank uncertainty — the long lanes
are blocked in the collective, not computing.
tests/ut/py/test_worker/test_startup_readiness.pyunder full-suite load; the module passes in isolation and the flake reproduces
on the merge base.
Follow-ups
Deliberately out of scope, each a separate change:
Per-process host log placement.
host.<pid>.logstays at the case rootrather than under
rankN/. It is a per-process artifact, not a per-dispatchone, and moving it requires
strace_timing._expand_log_sourceto stoprelying on a non-recursive
host.*.logglob ofoutput_prefix.hbg L3 end-to-end coverage. Both
host_build_graphL3 scene tests aredevice_count: 1and override_run_and_validate_l3to discard thediagnostic arguments, so no existing case exercises the hbg path. Needs a new
multi-device hbg L3 case.
Collapsible Rank tracks. A Chrome-trace JSON has only
processandthreadlevels, so Rank and view compete for the outer one; view keeps it,and a Rank cannot be collapsed as a group. Three levels require emitting
Perfetto protobuf (
TrackDescriptor.parent_uuid).Timeline origin and anchor placement. The single-file origin is still the
opening anchor rather than the minimum of all events, and the two runtimes
open the calibrated interval at different points. Both are prerequisites for
putting the Host swimlane ([Feature] Host swimlane (L3/L4) — the missing third DFX timeline #1708) on the same timeline as the chip swimlanes.
Cross-Rank dependency flows. This PR aligns and co-displays Rank-local timelines, but does not emit dependency flows between Ranks. Existing dependency and completion flows remain Rank-local and are namespaced during merge. Notify/wait and remote load/store causality will be added by a follow-up PR.