Add: A5 RTT die-preflight scheduler placement

CMakeLists.txt

@@ -76,6 +76,11 @@ if(SKBUILD_MODE)
     # sanitizer build is requested.
     install(DIRECTORY ${CMAKE_SOURCE_DIR}/cmake/
             DESTINATION simpler_setup/_assets/cmake)
+    # The public RTT preflight CLI builds and invokes this small hardware
+    # backend from either a source checkout or an installed wheel.
+    install(DIRECTORY ${CMAKE_SOURCE_DIR}/tools/cann-examples/aicpu-device-query/
+            DESTINATION simpler_setup/_assets/tools/cann-examples/aicpu-device-query
+            PATTERN "build" EXCLUDE)
     install(DIRECTORY ${CMAKE_SOURCE_DIR}/build/lib/
             DESTINATION simpler_setup/_assets/build/lib
             OPTIONAL

simpler_setup/tools/README.md

@@ -18,6 +18,7 @@ no repo checkout required.
 - **[phase_time_split](#phase_time_split)** — the same `bind phase=` markers split into on-CPU and off-CPU per phase, from per-thread CPU clocks, with cold and warm binds reported separately
 - **[dump_viewer](#dump_viewer)** — inspect / export args dumps (see [docs/args-dump.md](../../docs/dfx/args-dump.md) for full workflow)
 - **[deps_viewer](#deps_viewer)** — `deps.json` (dep_gen) → text or pan/zoom HTML dependency graph
+- **[rtt_die_preflight](#rtt_die_preflight)** — preflight: write/merge `aicpu_rtt_die_plan.json` (runtime only reads it)
 
 For CLIs that allow an omitted input, auto-detection paths
 (`outputs/*/chip_swimlane_records.json`, `outputs/*/args_dump/`) are resolved
@@ -795,6 +796,44 @@ For batch-run hardware regression, see the dev-only script
 
 ---
 
+## rtt_die_preflight
+
+Preflight CLI only: invoke `aicpu-device-query`'s multi-thread A5 COND RTT mode
+and atomically write/merge `build/config/aicpu_rtt_die_plan.json`. Runtime never
+probes RTT during an ordinary run; Host validates schema v2 and caches the JSON
+lookup for the `DeviceRunner` lifetime, then Device adopts affinity→logical
+before balanced contiguous assignment. Missing/invalid data emits one warning
+for that exact topology and uses the same balanced contiguous assignment
+without remapping. Non-four-scheduler configurations always use the contiguous
+default.
+
+The probe serializes the four pinned schedulers after a shared ready barrier,
+warms both dies, and returns nine rounds of raw totals (256 COND loads per
+core). The CLI ranks each scheduler by the median paired die0-minus-die1 delta;
+it does not use `AicpuLogicalCpu::die_id` as a proxy. In one measured 1/3 CPU
+placement, S0 and S3 are the die0/die1 anchors while the middle S1/S2 pair is
+close and may swap. Those affinity IDs are machine-specific. Establish each
+machine's two clear endpoint anchors from its reference measurement; across
+repeated probes require only the die0 anchor to remain in logical 0/1 and the
+die1 anchor in logical 2/3. The two middle affinity slots need not keep a stable
+order.
+
+Schema-v1 plans are not upgraded in place because they contain rounded,
+single-pass measurements. Remove or archive one before generating its v2
+replacement.
+
+```bash
+task-submit --device auto --device-num 1 --run \
+  'python -m simpler_setup.tools.rtt_die_preflight --device "$TASK_DEVICE" --probe'
+
+# Optional offline mode requires explicit, measured topology inputs and writes
+# plan_source="manual":
+python -m simpler_setup.tools.rtt_die_preflight --device 0 \
+  --soc Ascend950PR_9599 --allowed-cpus 3,4,5,6,8 --deltas=100,-50,-80,20
+```
+
+---
+
 ## Output File Reference
 
 | File | Tool | Purpose | Format |

simpler_setup/tools/__init__.py

@@ -17,4 +17,5 @@
 - ``dump_viewer``           : inspect args dumps
 - ``strace_timing``         : per-stage / per-round timing from [STRACE] log markers
 - ``hbg_bind_phases``       : per-phase host_build_graph bind statistics from `bind phase=` markers
+- ``rtt_die_preflight``     : probe A5 COND RTT and write the scheduler die plan
 """