Open RTT is a small open-source RAM transport for embedded targets and debugger-side host tools. It gives firmware a lightweight text channel without consuming a UART, USB CDC endpoint, or extra board wiring. The target exposes a fixed control block plus two ring buffers in RAM; the host reads and writes that RAM through the active debug probe.
The current repository contains:
firmware/rtt: portable target-side C libraryhost/dss: TI DSS host backendexamples/f28p65x: minimal C2000 integration exampletests: native tests and a basic toolchain check script
Open RTT is intentionally simple:
- one control block in RAM
- one up ring (
target -> host) - one down ring (
host -> target) - ASCII payloads stored in 16-bit cells
- line-oriented command path from host to target
It is inspired by the RTT style of debugger-assisted I/O, but the protocol and implementation in this repository are intentionally explicit and easy to reimplement for other debuggers and MCU families.
- early bring-up when no serial path is available yet
- interactive commands over JTAG or SWD
- debug logs without dedicating board pins
- a common transport shape for TI C2000, MSPM0, MSP430, Cortex-M, Cortex-R, and other targets
firmware/rtt/include/rtt.h: public target APIfirmware/rtt/include/rtt_protocol.h: wire-visible memory layoutfirmware/rtt/src: target implementationhost/dss/rtt_host.js: debugger-side polling host for CCS DSSexamples/f28p65x/linker_snippet.cmd: linker section exampleexamples/f28p65x/rtt_demo.c: minimal echo applicationtests/native/test_rtt.c: native behavior tests
- Add these target files to your firmware build:
firmware/rtt/src/rtt.cfirmware/rtt/src/rtt_ringbuf.cfirmware/rtt/src/rtt_port.c- include path
firmware/rtt/include
- Reserve RAM for
.rtt_blockand.rtt_buf. - Call
rtt_init()during system startup. - Use
rtt_write_line()orrtt_write_char()to publish output. - Use
rtt_read_line()orrtt_read_char()to consume host input. - Start the host backend from DSS:
dss.sh host/dss/rtt_host.js \
--ccxml /path/to/target_xds110.ccxml \
--symbols /path/to/app.out \
--part F28P65If the symbol table is unavailable, use --cb-addr <native-address> instead of --symbols.
- docs/README.md: documentation index
- docs/protocol_spec.md: control block and ring format
- docs/FIRMWARE_INTEGRATION.md: target-side integration guide
- docs/DEBUGGER_BACKEND_PORTING.md: host/backend design and porting notes
- docs/USAGE.md: end-to-end usage and troubleshooting
- docs/CONTRIBUTING.md: contribution workflow
- fixed protocol version
0x00020000 - 92-byte control block
- 16-bit transport cells so C28x word-addressed targets are handled cleanly
- host-side target profiles for several TI MCU families in the DSS backend
- whole-line admission on the down ring so partial commands are not injected into firmware
- single channel only
- ASCII payloads only
- no binary framing yet
- no timestamps or message metadata
- DSS backend is the only host backend currently checked in
This project is intended to be maintained as an open-source transport library. Contributions are welcome for:
- new debugger backends
- new MCU integration examples
- protocol review and hardening
- tests and CI improvements
- documentation fixes and translations
If you want to contribute code, examples, or target support, start with docs/CONTRIBUTING.md. Backend ports for ST-Link, OpenOCD, pyOCD, J-Link, ESP-Prog, and similar tools are especially useful.