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What does macOS's Thunderbolt stack do to bring USB4 up on the T6034 that Linux does not do yet?
Use ipsw on the Mac15,11 kernelcache (kernelcache.release.mac15j, extracted earlier to the session scratchpad) to find the kexts for the NHI, the ACIO, the ATC / Type-C PHY and the PCIe tunnel root ports. Work out their init sequence on the T6034: tunables, firmware or mailbox handshakes, power and reset order, and anything specific to the T603x generation compared with the T6030 and T6021 paths Linux already has.
The answer lists the steps Linux is missing, each tied to where in Linux it would go.
macOS runs the same NHI, MxWrap, T8122 PHY and T8122 PCIe-C kexts on the T6030 and the T6031/T6034. Every T6030/T6034 difference is in Linux's hw table and DT.
The code confirms the T6034 ACIO is an MxWrap IOP:
CPU_CTRL RUN: 0x10 at cpu+0x28.
LSTX: rc+0x0c = 3 (cable connected) or 2 (no cable).
Ten ADT tunable tables are applied only after that.
Linux's t6031 path does none of the first three (apple.c:154-160).
m1n1 swaps the hi_up_tx_desc and hi_up_rx_desc NHI tunable offsets on every chip except T8142 (kboot.c:1556-1558).
macOS waits up to 10 s for the CIO reconfigure to complete. Linux waits 100 ms.
The PCIe tunnel root port needs a T6031 tunnel DT, a T8122 MSI map and reset table, and apcie-common tunables. The doc lists 19 gaps, each with its file:line.
Activity
hungbenjamin402 commentedon Nov 9, 2026
Findings: https://github.com/hungbenjamin402/linux-aurora/blob/research/macos-usb4/research/macos-usb4.md
cpu+0x28.rc+0x0c = 3 (cable connected) or 2 (no cable).rc+0xa8 bits 30:24 == 1, polled every 5 ms.apple.c:154-160).hi_up_tx_descandhi_up_rx_descNHI tunable offsets on every chip except T8142 (kboot.c:1556-1558).apcie-commontunables. The doc lists 19 gaps, each with its file:line.