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Fix #507#510

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gussmith23 wants to merge 6 commits intomainfrom
gus/507
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Fix #507#510
gussmith23 wants to merge 6 commits intomainfrom
gus/507

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@gussmith23 gussmith23 commented Jun 24, 2025

Closes #507

Adds test showing ability to do (d-a)^2

While debugging, it was useful to hardcode some values to try and get this to work:

modified   architecture_descriptions/xilinx_ultrascale_plus.yml
@@ -248,7 +248,7 @@ implementations:
 
             { name: CLK, direction: input, bitwidth: 1, value: clk },
             { name: D, direction: input, bitwidth: 27, value: (choose D (extract 26 0 C)) },
-            { name: INMODE, direction: input, bitwidth: 5, value: INMODE },
+            { name: INMODE, direction: input, bitwidth: 5, value: "(bv #b01100 5)" },
             { name: MULTSIGNIN, direction: input, bitwidth: 1, value: (bv 0 1) },
             { name: OPMODE, direction: input, bitwidth: 9, value: OPMODE },
             { name: PCIN, direction: input, bitwidth: 48, value: (choose (zero-extend C (bitvector 48)) (bv 0 48)) },
@@ -268,10 +268,10 @@ implementations:
         parameters: [
           # Set to AREG given that we don't use cascade paths.
           { name: ACASCREG, value: (zero-extend AREG (bitvector 32)) },
-          { name: ADREG, value: (zero-extend ADREG (bitvector 32)) },
+          { name: ADREG, value: (zero-extend (bv 1 1) (bitvector 32)) },
           { name: ALUMODEREG, value: (zero-extend ALUMODEREG (bitvector 32)) },
           { name: AMULTSEL, value: (choose (bv 0 5) (bv 2 5)) },
-          { name: AREG, value: (zero-extend AREG (bitvector 32))},
+          { name: AREG, value: (zero-extend (bv 1 1) (bitvector 32))},
           # NO_RESET
           { name: AUTORESET_PATDET, value: (bv 3 5) },
           # RESET
@@ -287,7 +287,7 @@ implementations:
           { name: CARRYINREG, value: (bv 0 32) },
           { name: CARRYINSELREG, value: (zero-extend CARRYINSELREG (bitvector 32)) },
           { name: CREG, value: (zero-extend CREG (bitvector 32)) },
-          { name: DREG, value: (zero-extend DREG (bitvector 32)) },
+          { name: DREG, value: (zero-extend (bv 1 1) (bitvector 32)) },
           { name: INMODEREG, value: (zero-extend INMODEREG (bitvector 32)) },
           { name: IS_ALUMODE_INVERTED, value: (bv 0 4) },
           { name: IS_CARRYIN_INVERTED, value: (bv 0 1) },
@@ -305,7 +305,7 @@ implementations:
           { name: IS_RSTM_INVERTED, value: (bv 0 1) },
           { name: IS_RSTP_INVERTED, value: (bv 0 1) },
           { name: MASK, value: (bv 0 48) },
-          { name: MREG, value: (zero-extend MREG (bitvector 32)) },
+          { name: MREG, value: (zero-extend (bv 1 1) (bitvector 32)) },
           { name: OPMODEREG, value: (zero-extend OPMODEREG (bitvector 32)) },
           { name: PATTERN, value: (bv 0 48) },
           # A

most notable being INMODE, which I set using Table 2-2 in the DSP manual.

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Cannot synthesize pre-adders?

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