GitHub - frontcover/Radar-Pulse-Sync: Verilog FPGA code for radar pulse sync · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Cmod-A7-Master.xdc		Cmod-A7-Master.xdc
FPGA.v		FPGA.v
Radar_Pulse_Sync_160us_40us_400ns.xpr		Radar_Pulse_Sync_160us_40us_400ns.xpr
Radar_Pulse_Sync_400ns_40us.xpr		Radar_Pulse_Sync_400ns_40us.xpr
Radar_Sync_500ns_CPI.v		Radar_Sync_500ns_CPI.v
Radar_Sync_500ns_NoCPI.v		Radar_Sync_500ns_NoCPI.v
TestDesign500ns_CPI_Pulse.xpr		TestDesign500ns_CPI_Pulse.xpr

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Verilog FPGA code for radar pulse sync

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