Improve SVE2 optimizations of SimdWinogradKernel3x3Block2x2SetInput - #898
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Add an NCHW (trans=0) SVE2 path that processes F tiles with contiguous loads, svuzp deinterleave, and predicated padding/tails instead of the scalar Base fallback. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
ermig1979
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August 20, 2026 10:40
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The SVE2 implementation of
SimdWinogradKernel3x3Block2x2SetInputused the scalar Base path for NCHW (trans = 0), so it was much slower than NEON.This change adds a vectorized NCHW path that processes
F = svcntw()tiles at a time:svld1loads of overlapping windows, thensvuzp1/svuzp2to deinterleave even/odd spatial positions (nosvld2/svld4)PadNose1/PadTail1/PadTail2)srcHeight < 4orsrcWidth < 4) still fall back to Basetrans = 1) is unchangedRelease notes for 7.2.165 list the improvement.
No macros were added.
Correctness was checked by cross-compiling for AArch64 and running under QEMU at three SVE lengths:
neoverse-n2:svcntw=4(128-bit)neoverse-v1:svcntw=8(256-bit)max/a64fx:svcntw=16(512-bit)Each length ran 248 cases (31 shapes × pad 0/1 × trans 0/1 × Base-vs-Sve2 and Neon-vs-Sve2), including AutoTest sizes such as
512x7x6,256x14x12,128x28x24, and64x56x48. All passed.