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Improve SVE2 optimizations of SimdSynetConvert32fTo8u - #896

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ermig1979 merged 1 commit into
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Aug 20, 2026
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Improve SVE2 optimizations of SimdSynetConvert32fTo8u#896
ermig1979 merged 1 commit into
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cursor/improve-sve2-synet-convert-32f-to-8u-eecf

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@ermig1979

@ermig1979 ermig1979 commented Aug 20, 2026

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The SVE2 NHWC channels == 3 path of SimdSynetConvert32fTo8u used gather/scatter, which is slower than the NEON implementation that processes interleaved RGB with sequential vector loads.

This change matches the NEON/AVX512 approach:

  • Build repeating scale/shift vectors [s0,s1,s2,s0,...] with svtbl
  • Convert consecutive float32 lanes and store consecutive bytes (svld1 / svst1b)
  • Handle the remainder with SVE predicates instead of scalar fallback

Release notes for 7.2.165 list the improvement.

Correctness was checked by cross-compiling for AArch64 and running under QEMU SVE2 at VL=128 (svcntw=4) and VL=512 (svcntw=16):

  • Standalone Base vs Simd::Sve2::SynetConvert32fTo8u: 228 cases, 0 failures (NHWC c=3 including tails, plus NCHW / other channel counts)
  • Test::SynetConvert32fTo8uAutoTest: all tests finished successfully
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Replace gather/scatter in the NHWC channels==3 path with sequential vector
loads and stores using a repeating per-channel scale/shift pattern.

Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
@ermig1979
ermig1979 marked this pull request as ready for review August 20, 2026 09:20
@ermig1979
ermig1979 merged commit ba9a494 into dev Aug 20, 2026
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