Improve SVE2 optimizations of classes ResizerByteArea1x1 and ResizerByteArea2x2 - #893
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Process full byte vectors in the 1x1 area row update instead of widening one int32 lane at a time, and vectorize horizontal reduction for 3/4 channels. For 2x2, pair same-channel neighbors with tbl/tbl2 and SVE2 svadalp, using a two-vector BGR step so channels 3 and 4 keep high utilization at 128-bit SVE length. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
ermig1979
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August 20, 2026 07:19
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Summary
ResizerByteArea1x1by loading fulluint8vectors, unpacking to int32, and multiplying by area weights, instead ofsvld1ub_s32(onlysvcntw()bytes per iteration). Horizontal reduction for 3/4 channels uses predicated int32 accumulation andsvst1b.ResizerByteArea2x2for channels 3 and 4: pair same-channel neighbors withsvtbl/svtbl2(nosvld3/svld4), sum 2x2 blocks with SVE2svadalp, then widen and multiply. BGR uses a two-vector step (AlignLoAny(2*VL, 6)) so 128-bit SVE processes 30 source bytes instead of 12.docs/2026.html.Test plan
./Test "-r=.." -fi=Resizer -tt=1 -ts=1— passed (x86 AVX-512 host vs Base), including Area (ArS) and AreaFast (ArF) for 1–4 channels. Elapsed 88.6 s.SimdSve2ResizerArea.cpp+SimdBaseResizerArea.cppfor AArch64+SVE2 and compared Sve2 vs BaseRunon 240 size/channel cases per vector length:sve-max-vq=1(16-byte VL): OKsve-max-vq=2(32-byte VL): OKsve-max-vq=4(64-byte VL): OK