Improve SVE2 optimizations of SimdSobelDy

[ermig1979]

Rewrite the ARM SVE2 implementation of SimdSobelDy so it is no longer slower than the NEON path.

The previous SVE2 version loaded half-width 16-bit lanes (svld1ub_s16) and processed only svcnth() pixels per iteration. The new path:

• loads full 8-bit SVE vectors
• uses SVE2 widening 1-2-1 horizontals (svaddlb / svaddlt / svmlalb / svmlalt)
• reorders even/odd 16-bit results with svzip1 / svzip2 and scalar stores (no structured svst2)
• reuses per-row horizontal sums across 2 and 4 output rows
• unrolls two vectors in the inner loop
• keeps first/last columns as scalar edge cases

docs/2026.html release 7.2.165 Improving section is updated. Test::SobelDyAutoTest extra SVE2 sizes now use svcntb().

Testing

• Native Test -fi=SobelDy (Base / SSE4.1 / AVX2 / AVX-512BW): passed
• Cross-compiled SVE2 vs Base under QEMU: 4758 cases at VL=16, 7638 at VL=32, 13398 at VL=64, and 4758 on neoverse-n2: all passed