feat: GPU-native CN TRT preprocessors + TRT perf phases 1-3 + CN residual caching#20

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SDTD_031_devfrom

feat/cn-trt-preprocessors-trt-perf

Commits on Jun 13, 2026

perf: add ControlNet profiler regions and CN-enabled benchmark mode
forkni
committed
fix: bypass offline orchestrator in CN benchmark activation
forkni
committed
perf: add CN residual caching with live cn_cache_interval control
forkni
committed
perf: add --cn-cache-interval flag to offline benchmark
forkni
committed
docs: add cn_cache_interval to td_config example (backend already wired)
forkni
committed
fix: filter benign TRT myelin tactic-skip spam from VAE engine builds
forkni
committed
refactor: share one TRT build-log filter to drop logger-mismatch warning
forkni
committed
feat: add scribble preprocessor, GPU-native standard_lineart, lazy RealESRGAN init
forkni
committed
feat: add GPU-native CN preprocessors (hed/scribble/normal_bae TRT), residency guard, autopreprocess registry
forkni
committed
fix: harden CN TRT preprocessors — NormalBae fallback init, dynamic shape alignment, error diagnostics, profile support
forkni
committed
fix: suppress TRT logger-mismatch warning in all build and load paths
forkni
committed
fix: align web demo CN preprocessors (scribble_tensorrt, tile passthrough)
forkni
committed
test: add manual GPU smoke test for self-building TRT preprocessors
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committed
perf: Phase 1 quick wins + Step 0 benchmark harness
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committed
perf: Phase 2 IPA event-sync+cache, ESRGAN lock shrink, CN antialias
forkni
committed
perf: Phase 3 TRT buffer LRU cache, direct GPU alloc, nvJPEG GPU decode
forkni
committed
feat: wire --save-goldens to ab_bench.py
forkni
committed
fix: harden UNet cache key + dedicated TRT preprocessor stream
forkni
committed
perf: eliminate per-frame D2H syncs + surface silent PIL round-trips in preprocessors
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committed

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feat: GPU-native CN TRT preprocessors + TRT perf phases 1-3 + CN residual caching#20

feat: GPU-native CN TRT preprocessors + TRT perf phases 1-3 + CN residual caching#20
forkni wants to merge 19 commits into
SDTD_031_devfrom
feat/cn-trt-preprocessors-trt-perf

Commits on Jun 13, 2026

perf: add ControlNet profiler regions and CN-enabled benchmark mode

fix: bypass offline orchestrator in CN benchmark activation

perf: add CN residual caching with live cn_cache_interval control

perf: add --cn-cache-interval flag to offline benchmark

docs: add cn_cache_interval to td_config example (backend already wired)

fix: filter benign TRT myelin tactic-skip spam from VAE engine builds

refactor: share one TRT build-log filter to drop logger-mismatch warning

feat: add scribble preprocessor, GPU-native standard_lineart, lazy RealESRGAN init

feat: add GPU-native CN preprocessors (hed/scribble/normal_bae TRT), residency guard, autopreprocess registry

fix: harden CN TRT preprocessors — NormalBae fallback init, dynamic shape alignment, error diagnostics, profile support

fix: suppress TRT logger-mismatch warning in all build and load paths

fix: align web demo CN preprocessors (scribble_tensorrt, tile passthrough)

test: add manual GPU smoke test for self-building TRT preprocessors

perf: Phase 1 quick wins + Step 0 benchmark harness

perf: Phase 2 IPA event-sync+cache, ESRGAN lock shrink, CN antialias

perf: Phase 3 TRT buffer LRU cache, direct GPU alloc, nvJPEG GPU decode

feat: wire --save-goldens to ab_bench.py

fix: harden UNet cache key + dedicated TRT preprocessor stream

perf: eliminate per-frame D2H syncs + surface silent PIL round-trips in preprocessors