The AG32 is a microcontroller with a small FPGA bolted to it. It's a real RV32IMAFC core with hard peripherals (UART, SPI, I²C, CAN, USB, Ethernet MAC, timers, ADC/DAC, GPIO), plus a small programmable fabric sitting between those peripherals and the pins:
| RISC-V MCU | FPGA fabric |
|---|---|
|
|
The fabric can be independent logic, a pin-routing layer for hard peripherals, or a memory-mapped coprocessor beside the MCU. The AG32 overview explains the device, naming, clocks, boot paths, packages, and documentation landscape.
The vendor architecture makes the fabric configurable glue between many hard peripheral signals and package pads. In principle that permits flexible UART placement, state machines in signal paths, memory-mapped custom peripherals, and runtime muxing. AGaMEMnon currently qualifies only the exact routes listed in the support matrix; a hard-peripheral register driver does not by itself prove a fabric or package-pin route. It's a bit like a Cypress PSoC, except the programmable part is an actual FPGA bolted to a RISC-V core.
flowchart LR
FW["RISC-V firmware"] --> MCU["RV32IMAFC MCU"]
MCU <--> AHB["AHB matrix"]
AHB <--> AHBP["AHB peripherals<br/>USB OTG · CRC · RCU · flash · SRAM"]
AHB <--> APB["AHB-to-APB bridge"]
APB <--> HARD["Hard peripherals<br/>UART · SPI · I²C · CAN · timers · RTC<br/>watchdogs · ADC · DAC · comparator · GPIO"]
RTL["Your Verilog"] --> FLOW["Yosys → nextpnr → AGaMEMnon bitgen"]
FLOW --> FABRIC["AGRV2K FPGA fabric<br/>LUTs · FFs · BRAM · routing"]
AHB <--> PORTS["FPGA AHB<br/>slave + master ports"]
PORTS <--> FABRIC
HARD <--> PINS["Package pins"]
FABRIC <--> PINS
classDef firmware fill:#2563eb,stroke:#1e40af,color:#fff
classDef mcu fill:#0f766e,stroke:#115e59,color:#fff
classDef fabric fill:#7c3aed,stroke:#5b21b6,color:#fff
classDef tools fill:#c2410c,stroke:#9a3412,color:#fff
classDef physical fill:#475569,stroke:#334155,color:#fff
class FW firmware
class MCU,AHB,AHBP,APB,HARD mcu
class RTL,FLOW tools
class PORTS,FABRIC fabric
class PINS physical
The AG32 has almost no English-language documentation. The 'normal' way to
build a bitstream is a Windows-only Altera Quartus II fork you fetch from a
Baidu Netdisk link (password 12ej), driving a black-box fabric back-end,
af.exe. There is no Linux path and no open format. Fuck you if you want to
use this chip as intended.
AGaMEMnon takes Verilog and produces a flashable AG32 fabric bitstream — synthesis, pack, place, route, bitstream generation, and programming, with no vendor binary in the path. It's an SDK for the RISC-V half of this chip. This is an open toolchain for a weird combination RISC-V microcontroller and FPGA.
This is IceStorm for a chip nobody has heard of. Verilog synthesizes, places, routes, and runs on real silicon: combinational and sequential logic, counters and state machines, clocking across the array, output to real pins, and the RISC-V core reading and writing the fabric over its memory bus. There's a writeup of how it works here.
Watch the video demo:
AGaMEMnon is a source-installable development preview; there is no
downloadable SDK release yet. The current hardware target is the
AG32VF303CCT6 LQFP-48 development board with AGRV2KL48 fabric, and
support is deliberately narrow and evidence-bounded. L100, L64, and Q32 builds
use recovered physical maps and warn that they are unqualified; unsupported
routes and hard-block modes fail closed instead of silently producing an image
outside the evidence boundary. The exact line is drawn in
the support matrix and
the hardware qualification record; known gaps
and prioritized work are in ROADMAP.md.
The open External-AHB path now includes a silicon-qualified combinational
slave: all 32 read-data lanes return 0x4147414d, HREADYOUT/HRESP complete
ready/OKAY transfers, and writes complete without changing the response. The
bounded writable boundary now qualifies a three-bit HADDR2-tagged posted
scratch register through the pure open flow, but not the full register bank, integrated reset, wait
states, or error responses. The distinction and retained hashes are documented in
the register-bank boundary and
the qualification record.
git clone https://github.com/bbenchoff/AGaMEMnon
cd AGaMEMnon
python3 -m pip install -e ".[programming]"
agamemnon doctor --no-hardwareAll required data is stored as normal Git objects; Git LFS is not required.
Try it without a board or FPGA toolchain — the repository contains a routed counter fixture:
agamemnon verify tests/fixtures/counter_ahb_routed.json --cycles 8Then create and run a first project:
agamemnon new hello --board ag32vf303-l48 # default template: fabric-free MCU blink
cd hello
agamemnon build # MCU-only -> needs just RISC-V GCC
agamemnon run --transport dap # run on a connected board (volatile SRAM)To see what makes the AG32 unusual, use --template mcu-fpga: its firmware
talks to a custom memory-mapped fabric register, and its build runs Yosys and
nextpnr.
Setup comes in tiers, and agamemnon doctor reports which one you are at:
Python 3.8+ alone covers inspection, conversion, and offline verification;
the bundled riscv-none-elf-gcc (or compatible riscv64-unknown-elf-gcc)
adds MCU firmware builds; Yosys and the AGRV2K
nextpnr backend add fabric builds; a CMSIS-DAP probe plus AGaMEMnon's
qualified OpenOCD (agamemnon install-openocd) adds programming. See
Installation.
The beginner-safe transport is SWD/DAP: it works on an untouched stock board and can recover one. The USB CDC uploader becomes the convenient application transport after its loader is installed, and the Pico-driven UART0 mask ROM is the flash-independent recovery path. Read Programming before any persistent write, and compare your board against known-good hardware first.
| Read | For |
|---|---|
| AG32 overview | the device, naming, clocks, boot paths, and vendor sources |
| Support matrix | exactly what is supported and silicon-qualified |
| Installation | toolchains and drivers on Windows, Linux, and macOS |
| Usage | the complete command reference |
| Projects | manifests, templates, and the project model |
| Programming | SWD/DAP, USB CDC, and UART transports and safety flow |
| Examples | runnable RTL, firmware, PCFs, and bitstream recipes |
| MCU SDK | the open HAL and its qualification state |
| MCU clocks | core versus fabric clocks, transition rules, and current limits |
| MCU pin routing | alternate-function semantics and silicon-backed route policy |
| Architecture | the recovered fabric, router, and bitstream internals |
| Bitstream format | compressed/raw containers, CRC, physical features, and selector policy |
| MCU External AHB | the qualified constant endpoint and remaining sequential register-bank boundary |
| MCU/fabric roadmap | unfinished AHB, interrupt, DMA, GPIO, and hard-block work |
| Hardware qualification | the silicon evidence boundary |
| Qualification reports | read-only, reviewable support-evidence intake |
| Roadmap | known limitations and prioritized work |
| Notices | provenance and the licensing boundary |
New hardware evidence is especially valuable. Read CONTRIBUTING.md before submitting code or qualification records, use SUPPORT.md when something does not behave as documented, and report security problems according to SECURITY.md. User-visible changes are recorded in CHANGELOG.md. Participation is governed by the code of conduct.
AGaMEMnon. I had 'AG' to work with, and something about 'MEMory'. I named it before Nolan's Odyssey came out. I am also mentally preparing for Marc Andreessen quoting Aeschylus when Trump finally dies.