drm/asahi: accept the T8122 25G83 mailbox compatible list

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@@ -2794,9 +2794,11 @@ F:	tools/asahi/apple-pwm-pm-tests.py
 F:	drivers/reset/reset-apple-cio.c
 F:	drivers/rtc/rtc-macsmc.c
 F:	drivers/soc/apple/*
+F:	tools/asahi/m3-uapi-*
 F:	drivers/soc/apple/clpc.kunitconfig
 F:	tools/asahi/pmp-bootargs-tests.rs
 F:	drivers/spi/spi-apple-test.c
+F:	tools/asahi/test-m3-uapi.py
 F:	drivers/spi/spi-apple.c
 F:	drivers/spmi/spmi-apple-controller.c
 F:	drivers/thermal/apple-pmp*

arch/arm64/configs/asahi.config

@@ -65,6 +65,7 @@ CONFIG_DRM=y
 CONFIG_DRM_ASAHI=m
 CONFIG_DRM_ASAHI_G15=y
 CONFIG_DRM_ASAHI_G16=y
+CONFIG_DRM_ASAHI_M3_T8122=y
 CONFIG_DRM_ADP=m
 CONFIG_DRM_APPLE=m
 CONFIG_DRM_APPLE_DCP_T8132=y

drivers/gpu/drm/asahi/Kconfig

@@ -79,6 +79,22 @@ config DRM_ASAHI_DEBUG_ALLOCATOR
 	  Say N unless you are debugging firmware structures or porting to a
 	  new firmware version.
 
+config DRM_ASAHI_M3_T8122
+	bool "M3 MacBook Air GPU runtime (T8122, 14.8.3 firmware)"
+	depends on DRM_ASAHI
+	# The runtime adopts the firmware's UAT through the G15 backend's handoff helpers.
+	depends on DRM_ASAHI_G15
+	select CRYPTO_LIB_SHA256
+	default n
+	help
+	  Build the M3 runtime that starts the GPU of the M3 MacBook Air
+	  (J613, J615) on the 14.8.3 GPU firmware the boot loader leaves
+	  loaded. On the listed Air boards it starts after the boot loader
+	  handed the GPU over and resource/firmware identity checks pass.
+	  asahi.t8122_start=0 keeps startup disabled for recovery. Unknown
+	  boards and firmware do not gain automatic admission. Other GPUs
+	  are not affected.
+
 config DRM_ASAHI_G15
 	bool "Apple M3 Pro/Max (G15) support"
 	depends on DRM_ASAHI

drivers/gpu/drm/asahi/debug.rs

@@ -54,6 +54,13 @@ pub(crate) enum DebugFlags {
     DeviceControlCh = 21,
     FwCtlCh = 22,
 
+    // Host submission/completion timestamps without verbose firmware tracing.
+    SubmitTiming = 23,
+    // Low-volume M3 command/geometry totals without per-IRQ printk.
+    M3SubmitSummary = 24,
+    // Per-slot retired timestamps, without enabling firmware ktrace.
+    M3PassTiming = 25,
+
     // 32-35: Allocator debugging
     FillAllocations = 32,
     DebugAllocations = 33,

drivers/gpu/drm/asahi/driver.rs

@@ -52,6 +52,7 @@ pub(crate) struct AsahiPlatformDriverData<'bound> {
     g17: Option<Arc<g17::Gpu>>,
     #[cfg(CONFIG_DRM_ASAHI_G16)]
     pub(crate) g16: Option<Arc<crate::g16::Gpu>>,
+    m3: Option<M3Backend>,
     /// Raw `struct device *` of the platform device. Stored once at probe
     /// time so the `Drop` impl can find the sysfs file on unregister.
     raw_dev: *mut bindings::device,
@@ -65,6 +66,11 @@ unsafe impl Send for AsahiPlatformDriverData<'_> {}
 // SAFETY: As above.
 unsafe impl Sync for AsahiPlatformDriverData<'_> {}
 
+#[cfg(CONFIG_DRM_ASAHI_M3_T8122)]
+type M3Backend = Arc<crate::m3::m3_drm::Backend>;
+#[cfg(not(CONFIG_DRM_ASAHI_M3_T8122))]
+type M3Backend = core::convert::Infallible;
+
 /// Holds a reference to the top-level GPU object.
 #[pin_data]
 pub(crate) struct AsahiDrmRegistrationData<'drm> {
@@ -245,6 +251,10 @@ impl platform::Driver for AsahiPlatformDriver {
             // Driver data is dropped after devres, so CPU control must happen in unbind.
             gpu.shutdown();
         }
+        #[cfg(CONFIG_DRM_ASAHI_M3_T8122)]
+        if let Some(m3) = this.m3.as_ref() {
+            m3.stop();
+        }
         this.close_binding();
     }
 
@@ -264,6 +274,8 @@ impl platform::Driver for AsahiPlatformDriver {
         let cfg = match info.ok_or(ENODEV)? {
             ProbeConfig::Legacy(cfg) => *cfg,
             ProbeConfig::G17(cfg) => return AsahiPlatformDriver::probe_g17(pdev, cfg),
+            #[cfg(CONFIG_DRM_ASAHI_M3_T8122)]
+            ProbeConfig::M3(crate::m3::Chip::T8122) => return AsahiPlatformDriver::probe_t8122(pdev),
             ProbeConfig::M3(chip) => return Err(crate::m3::refuse_probe(pdev, *chip)),
             #[cfg(CONFIG_DRM_ASAHI_M5)]
             ProbeConfig::M5 => return AsahiPlatformDriver::probe_m5(pdev),
@@ -351,6 +363,7 @@ impl platform::Driver for AsahiPlatformDriver {
             _device: reg.device().into(),
             _reg: reg,
             g17: None,
+            m3: None,
             #[cfg(CONFIG_DRM_ASAHI_G16)]
             g16: None,
             raw_dev,
@@ -388,6 +401,7 @@ impl AsahiPlatformDriver {
             _device: reg.device().into(),
             _reg: reg,
             g17: None,
+            m3: None,
             #[cfg(CONFIG_DRM_ASAHI_G16)]
             g16: None,
             raw_dev: core::ptr::null_mut(),
@@ -396,6 +410,46 @@ impl AsahiPlatformDriver {
         })
     }
 
+    /// The M3 MacBook Air (T8122): the M3 runtime, started only when its identity gate, the
+    /// backend selection and the start experiment (`asahi.t8122_start=1`) admit it; otherwise
+    /// the probe is refused as without the runtime.
+    #[cfg(CONFIG_DRM_ASAHI_M3_T8122)]
+    fn probe_t8122<'bound>(
+        pdev: &'bound platform::Device<Core<'_>>,
+    ) -> Result<AsahiPlatformDriverData<'bound>> {
+        let soc = crate::m3::t8122_admitted(pdev)?;
+        // SAFETY: The admitted M3 GPU's UAT outputs 42-bit physical addresses.
+        unsafe { pdev.dma_set_mask_and_coherent(DmaMask::try_new(42)?)? };
+        let resources = regs::Resources::new(pdev)?;
+        let drm = drm::UnregisteredDevice::<AsahiDrmDriver>::new(pdev, Ok(()))?;
+        let binding = unsafe { crate::binding::Owner::new(pdev.as_ref(), &drm)? };
+        let backend = crate::m3::m3_drm::Backend::start(pdev, &drm, soc)?;
+        let gpu = backend.clone() as Arc<dyn gpu::Gpu>;
+        let data = try_pin_init!(AsahiDrmRegistrationData { gpu, resources });
+        // SAFETY: The registration is stored and unregistered by platform data destruction,
+        // which drops the runtime with it.
+        let reg = match unsafe { drm::Registration::new(pdev.as_ref(), drm, data, 0) } {
+            Ok(reg) => reg,
+            Err(error) => {
+                backend.stop();
+                return Err(error);
+            }
+        };
+        dev_info!(pdev.as_ref(), "M3: firmware ready; common DRM GEM/VM frontend registered\n");
+        Ok(AsahiPlatformDriverData {
+            binding,
+            #[cfg(CONFIG_DRM_ASAHI_G16)]
+            g16: None,
+            _device: reg.device().into(),
+            _reg: reg,
+            g17: None,
+            m3: Some(backend),
+            raw_dev: core::ptr::null_mut(),
+            raw_stats: core::ptr::null_mut(),
+            stats: None,
+        })
+    }
+
     fn probe_g17<'bound>(
         pdev: &'bound platform::Device<Core<'_>>,
         cfg: &'static g17::Config,
@@ -451,6 +505,7 @@ impl AsahiPlatformDriver {
             _device: reg.device().into(),
             _reg: reg,
             g17: Some(gpu),
+            m3: None,
             #[cfg(CONFIG_DRM_ASAHI_G16)]
             g16: None,
             raw_dev,
@@ -486,6 +541,7 @@ impl AsahiPlatformDriver {
             _device: reg.device().into(),
             _reg: reg,
             g17: None,
+            m3: None,
             #[cfg(CONFIG_DRM_ASAHI_G16)]
             g16: None,
             raw_dev: core::ptr::null_mut(),
@@ -524,6 +580,7 @@ impl AsahiPlatformDriver {
             _device: reg.device().into(),
             _reg: reg,
             g17: None,
+            m3: None,
             g16: Some(gpu),
             raw_dev,
             raw_stats,
@@ -579,6 +636,7 @@ impl AsahiPlatformDriver {
                 _device: reg.device().into(),
                 _reg: reg,
                 g17: None,
+                m3: None,
                 #[cfg(CONFIG_DRM_ASAHI_G16)]
                 g16: None,
                 raw_dev: core::ptr::null_mut(),
@@ -608,5 +666,9 @@ impl Drop for AsahiPlatformDriverData<'_> {
             // Also covers failure to allocate platform driver data after the probe body returned.
             gpu.shutdown();
         }
+        #[cfg(CONFIG_DRM_ASAHI_M3_T8122)]
+        if let Some(m3) = self.m3.as_ref() {
+            m3.stop();
+        }
     }
 }

drivers/gpu/drm/asahi/file.rs

@@ -282,6 +282,9 @@ pub(crate) struct File {
     mem: Arc<memacct::Client>,
     /// Completed engine time, retained by queues after handle destruction.
     usage: Arc<crate::usage::Client>,
+    /// Largest size this file has asked GET_PARAMS for the global parameters with
+    /// ([`gpu::Gpu::admit_vm`]).
+    params_size: core::sync::atomic::AtomicU64,
     /// The queues were drained once for an exiting task.
     drained: AtomicBool,
 }
@@ -376,6 +379,7 @@ impl File {
                 (*slot).user_range = user_range;
                 addr_of_mut!((*slot).mem).write(mem);
                 addr_of_mut!((*slot).usage).write(usage);
+                addr_of_mut!((*slot).params_size).write(core::sync::atomic::AtomicU64::new(0));
                 addr_of_mut!((*slot).drained).write(AtomicBool::new(false));
                 Ok(())
             })
@@ -480,6 +484,9 @@ impl File {
             core::slice::from_raw_parts(core::ptr::from_ref(&params).cast::<u8>(), size)
         })?;
 
+        file.inner()
+            .params_size
+            .fetch_max(data.size, core::sync::atomic::Ordering::Relaxed);
         Ok(0)
     }
 
@@ -551,6 +558,13 @@ impl File {
             // Every other runtime here reports DRM_ASAHI_GPU_HAL_LEGACY.
             return Err(EINVAL);
         }
+        reg_data.gpu.admit_vm(
+            device.as_ref().as_ref(),
+            file.inner()
+                .params_size
+                .load(core::sync::atomic::Ordering::Relaxed),
+            data.flags,
+        )?;
 
         let kernel_range = data.kernel_start..data.kernel_end;
         let user_range = file.inner().user_range.clone();
@@ -647,7 +661,7 @@ impl File {
         }
         let dummy_mapping = dummy_obj.map_at(
             &vm,
-            gpu.uat_geometry().unk_page(),
+            gpu.unknown_page(),
             mmu::PROT_GPU_SHARED_RW,
             true,
         )?;
@@ -1378,9 +1392,15 @@ impl File {
             cls_pr_debug!(Errors, "queue_create: Invalid priority\n");
             return Err(EINVAL);
         }
-        // HIGH has only been run on G17; G13 and G14 keep refusing it.
+        // Keep support tied to a backend and admitted profile. G13/G14 and
+        // unqualified M3 profiles retain their previous rejection.
+        let high_supported = reg_data.gpu.as_any().is::<crate::g17::Gpu>();
+        #[cfg(CONFIG_DRM_ASAHI_M3_T8122)]
+        let high_supported = high_supported || reg_data.gpu.as_any()
+            .downcast_ref::<crate::m3::m3_drm::Backend>()
+            .is_some_and(|gpu| gpu.supports_high_priority());
         if data.priority == uapi::drm_asahi_priority_DRM_ASAHI_PRIORITY_HIGH
-            && !reg_data.gpu.as_any().is::<crate::g17::Gpu>()
+            && !high_supported
         {
             cls_pr_debug!(
                 Errors,

drivers/gpu/drm/asahi/float.rs

@@ -44,16 +44,16 @@ struct F32U {
 }
 
 impl F32 {
-    /// Return the IEEE-754 binary32 representation.
-    pub(crate) const fn to_bits(self) -> u32 {
-        self.0
-    }
-
     /// Convert a raw 32-bit representation into an F32
     pub(crate) const fn from_bits(u: u32) -> F32 {
         F32(u)
     }
 
+    /// Convert to the raw IEEE 754 bits.
+    pub(crate) const fn to_bits(self) -> u32 {
+        self.0
+    }
+
     // Convert a `f32` value into an F32
     //
     // This must ONLY be used in const context. Use the `f32!{}` macro to do it safely.

drivers/gpu/drm/asahi/g15/mod.rs

@@ -69,10 +69,10 @@ mod pools;
 mod power;
 mod queue;
 mod recovery;
-mod regs;
+pub(crate) mod regs;
 mod slots;
 mod timestamp;
-mod uat;
+pub(crate) mod uat;
 mod vm;
 mod wire;
 

drivers/gpu/drm/asahi/g15/regs.rs

@@ -152,6 +152,21 @@ impl Mapping {
     pub(crate) fn phys(&self) -> u64 {
         self.phys
     }
+
+    /// Cleans the whole mapping to the point of coherency when it is the kernel's cacheable
+    /// mapping of reserved System RAM ([`Self::region`]); device and write-combined mappings
+    /// need nothing.
+    pub(crate) fn clean_poc(&self) {
+        if self.kind != Kind::WriteBack {
+            return;
+        }
+        let start = self.raw.addr();
+        // SAFETY: `start..start + maxsize` is this live mapping; cleaning a cacheable range has
+        // no other effect.
+        unsafe {
+            bindings::dcache_clean_poc(start as _, (start + self.raw.size()) as _);
+        }
+    }
 }
 
 impl Drop for Mapping {

drivers/gpu/drm/asahi/g15/uat.rs

@@ -202,16 +202,41 @@ pub(crate) struct Window {
 impl Window {
     /// Maps the UAT handoff regions ([`Mapping::region`]).
     pub(crate) fn new(adt: &super::adt::GpuAdt) -> Result<Self> {
+        Self::from_regions(adt.handoff.start, adt.ttbs.start, adt.tables.start, adt.shared_l2.start)
+    }
+
+    /// Maps the UAT handoff regions at the given physical addresses: the handoff page, the
+    /// TTBAT, the firmware kernel root and the shared L2 page. The M3 T8122 runtime takes them
+    /// from its admitted reserved-memory regions.
+    pub(crate) fn from_regions(handoff: u64, ttbs: u64, root: u64, shared_l2: u64) -> Result<Self> {
         Ok(Self {
-            handoff: Mapping::region(adt.handoff.start, hw::HANDOFF_SIZE as usize)?,
-            ttbs: Mapping::region(adt.ttbs.start, hw::TTBS_SIZE as usize)?,
-            root: Mapping::region(adt.tables.start, hw::PAGE as usize)?,
-            shared_l2: Mapping::region(adt.shared_l2.start, hw::SHARED_L2_SIZE as usize)?,
+            handoff: Mapping::region(handoff, hw::HANDOFF_SIZE as usize)?,
+            ttbs: Mapping::region(ttbs, hw::TTBS_SIZE as usize)?,
+            root: Mapping::region(root, hw::PAGE as usize)?,
+            shared_l2: Mapping::region(shared_l2, hw::SHARED_L2_SIZE as usize)?,
             image: KVec::from_elem(0u64, ENTRIES, GFP_KERNEL)?,
             snapshot: KVec::from_elem(0u64, ENTRIES, GFP_KERNEL)?,
         })
     }
 
+    /// [`Self::sync_range`] over the whole host window, then [`Self::clean_tables`].
+    pub(crate) fn sync_all(&mut self, uat: &mmu::Uat) -> Result {
+        self.sync_inner(uat, None)?;
+        self.clean_tables();
+        Ok(())
+    }
+
+    /// Cleans the firmware-walked pages this window writes (the kernel root, the shared L2,
+    /// the TTBAT and the handoff page) to the point of coherency. Only a region that is
+    /// reserved System RAM, mapped cacheable, has anything to clean: the UAT walker does not
+    /// snoop the CPU caches. The M3 T8122 runtime calls it after [`Self::bootstrap`].
+    pub(crate) fn clean_tables(&self) {
+        for map in [&self.root, &self.shared_l2, &self.ttbs, &self.handoff] {
+            map.clean_poc();
+        }
+        mb();
+    }
+
     /// Cold-start check: all 128 TTBAT words are zero.
     pub(crate) fn ttbat_is_clear(&self) -> Result<bool> {
         let t = self.ttbs.io();

drivers/gpu/drm/asahi/gpu.rs

@@ -361,6 +361,14 @@ pub(crate) trait Gpu: Send + Sync {
     fn base_clock_hz(&self) -> u32;
     /// Return the GPU address space geometry.
     fn uat_geometry(&self) -> mmu::UatGeometry;
+    /// Admit a client's parameter ABI before creating its VM.
+    fn admit_vm(&self, _dev: &kernel::device::Device, _params_size: u64, _flags: u32) -> Result {
+        Ok(())
+    }
+    /// GPU VA of each VM's dummy page, which must match the address the firmware was given.
+    fn unknown_page(&self) -> u64 {
+        self.uat_geometry().unk_page()
+    }
     /// Create a new `Vm` with the given range reserved for kernel-managed objects.
     fn new_vm(&self, kernel_range: Range<u64>) -> Result<mmu::Vm>;
     /// Create a VM charged to a DRM file when the backend bounds retained bindings.