arm64: dts: apple: t6041-j616c: describe the GPU (stacked on #914)

Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml

@@ -20,6 +20,7 @@ properties:
       - enum:
           - apple,abbey-pmic
           - apple,baku-pmic
+          - apple,chapel-pmic
           - apple,maverick-pmic
           - apple,sera-pmic
           - apple,stowe-pmic

arch/arm64/boot/dts/apple/Makefile

@@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_APPLE) += t6034-j516m.dtb
 dtb-$(CONFIG_ARCH_APPLE) += t6040-j614s.dtb
 dtb-$(CONFIG_ARCH_APPLE) += t6040-j616s.dtb
 dtb-$(CONFIG_ARCH_APPLE) += t6040-j616s-tether.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6041-j616c.dtb
 dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb
 dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb
 dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb

arch/arm64/boot/dts/apple/t6040.dtsi

@@ -205,6 +205,22 @@
 			#cooling-cells = <2>;
 		};
 
+#ifdef T6041_SIX_CORE_P_CLUSTERS
+		/* T6041 (t6041.dtsi): the sixth core, in ADT order */
+		cpu_p05: cpu@10105 {
+			compatible = "apple,brava-p";
+			device_type = "cpu";
+			reg = <0x0 0x10105>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_p0>;
+			operating-points-v2 = <&opp_p0>;
+			capacity-dmips-mhz = <1024>;
+			performance-domains = <&cpufreq_p0>;
+			#cooling-cells = <2>;
+		};
+#endif
+
 		cpu_p10: cpu@10200 {
 			compatible = "apple,brava-p";
 			device_type = "cpu";
@@ -269,6 +285,22 @@
 			performance-domains = <&cpufreq_p1>;
 			#cooling-cells = <2>;
 		};
+
+#ifdef T6041_SIX_CORE_P_CLUSTERS
+		/* T6041 (t6041.dtsi): the sixth core, in ADT order */
+		cpu_p15: cpu@10205 {
+			compatible = "apple,brava-p";
+			device_type = "cpu";
+			reg = <0x0 0x10205>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_p1>;
+			operating-points-v2 = <&opp_p1>;
+			capacity-dmips-mhz = <1024>;
+			performance-domains = <&cpufreq_p1>;
+			#cooling-cells = <2>;
+		};
+#endif
 	};
 
 	l2_cache_e: l2-cache-cluster0 {

arch/arm64/boot/dts/apple/t6041-j616c.dts

@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * MacBook Pro (16-inch, M4 Max)
+ *
+ * target-type: J616C
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6041.dtsi"
+#include "t604x-j614-j616.dtsi"
+
+/ {
+	compatible = "apple,j616c", "apple,t6041", "apple,arm-platform";
+	model = "Apple MacBook Pro (16-inch, M4 Max)";
+
+	/* aura opens a co-processor's DAPF only if it finds its alias here. */
+	aliases {
+		aop = &aop;
+		isp = &isp;
+		mtp = &mtp;
+	};
+};
+
+&smc {
+	smc_gpio_low: gpio@67700000 {
+		compatible = "apple,smc-low-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+/* ADT /arm-io/wlan module-instance */
+&wifi0 {
+	brcm,board-type = "apple,hostomel";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,hostomel";
+};
+
+&panel {
+	compatible = "apple,panel-j616", "apple,panel-mini-led", "apple,panel";
+	width-mm = <345>;
+	height-mm = <223>;
+	adj-height-mm = <216>;
+};
+
+&aop_audio {
+	apple,chassis-name = "J616";
+};
+
+&sound {
+	compatible = "apple,j616-macaudio", "apple,macaudio";
+	model = "MacBook Pro J616";
+};
+
+&sound_jack {
+	compatible = "apple,j616-macaudio-jack", "apple,macaudio";
+	model = "MacBook Pro J616 Jack";
+};
+
+/*
+ * The AFE and STM resets are SMC GPIOs here, not the J616s's gp1c sequence, and
+ * the MTP works without the J616s's ring transport.
+ */
+&mtp_hid {
+	/delete-property/ apple,afe-smc;
+	compatible = "apple,dockchannel-hid";
+	apple,afe-reset-gpios = <&smc_gpio_low 0x19 GPIO_ACTIVE_LOW>;
+	apple,stm-reset-gpios = <&smc_gpio_low 0x1a GPIO_ACTIVE_LOW>;
+};
+
+&mtp_mt {
+	firmware-name = "apple/tpmtfw-j616c.bin";
+	apple,power-method = <2>;
+};
+
+/*
+ * Per-device factory data from this Mac's own iBoot system container: the
+ * sealed calibration and the sealed root key.
+ */
+&mesa {
+	firmware-name = "apple/mesacal-j616c.bin", "apple/msrk-j616c.bin";
+};
+
+/*
+ * The other NUB SPMI buses hold a Chapel at 0xb and a Spitfire at 0x9
+ * (nub-spmi1), and Portiers at 0xa and 0xb (nub-spmi2), not the J616s's
+ * Abbeys at 0xe.
+ */
+&nub_spmi1 {
+	/delete-node/ pmic@e;
+
+	pmic@b {
+		compatible = "apple,chapel-pmic", "apple,spmi-nvmem";
+		reg = <0xb SPMI_USID>;
+	};
+};
+
+/* Nothing on nub-spmi2 has a binding yet. */
+/delete-node/ &nub_spmi2;
+
+/*
+ * iBoot moves the ISP firmware from boot to boot on this machine, so the
+ * J616s placement does not hold. Keep the camera off until the boot loader
+ * fills it in.
+ */
+&isp {
+	status = "disabled";
+};
+
+/*
+ * The GPU (ADT gpu,t6041) has four clusters: one opp-microvolt cell per
+ * cluster (ADT /arm-io/sgx perf-states to perf-states3). The loader fills
+ * these placeholders, the CS and AFR tables and the memory regions.
+ */
+&gpu {
+	compatible = "apple,agx-t6041";
+};
+
+&gpu_opp {
+	opp00 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp01 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp02 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp03 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp04 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp05 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp06 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp07 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp08 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp09 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp10 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp11 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp12 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp13 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp14 {
+		opp-microvolt = <0 0 0 0>;
+	};
+	opp15 {
+		opp-microvolt = <0 0 0 0>;
+	};
+};
+
+/*
+ * The per-unit USB3 PHY values of this machine's ADT (auspll, cio4pll,
+ * aus40cmn-shm); every other tunable is the J616s's.
+ */
+
+&atcphy0 {
+	apple,tunable-auspll =
+		<0x3224 0x00000c00 0x00000800>,
+		<0x3230 0x0000001f 0x0000000f>,
+		<0x3240 0x07d8007f 0x04000049>,
+		<0x32b0 0x0b800000 0x01800000>,
+		<0x32e8 0x00060001 0x00040001>,
+		<0x3338 0x0f800000 0x07800000>;
+
+	apple,tunable-cio4pll =
+		<0x3a30 0x0000001f 0x0000000f>,
+		<0x3a4c 0x0000fe7f 0x00005421>,
+		<0x3ab0 0x00700000 0x00300000>,
+		<0x3ae8 0x00060000 0x00020000>;
+};
+
+&atcphy1 {
+	apple,tunable-cio4pll =
+		<0x3a30 0x0000001f 0x0000000f>,
+		<0x3a4c 0x0000fe7f 0x00005421>,
+		<0x3ab0 0x00700000 0x00300000>,
+		<0x3ae8 0x00060000 0x00020000>;
+};
+
+&atcphy2 {
+	apple,tunable-aus40cmn-shm =
+		<0xa04 0x0000007c 0x00000050>;
+
+	apple,tunable-cio4pll =
+		<0x3a30 0x0000001f 0x0000000f>,
+		<0x3a4c 0x0000fe7f 0x00005420>,
+		<0x3ab0 0x00700000 0x00300000>,
+		<0x3ae8 0x00060000 0x00020000>;
+};

arch/arm64/boot/dts/apple/t6041.dtsi

@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple T6041 "M4 Max" SoC
+ *
+ * The blocks t6040.dtsi describes sit at the same addresses, with the same
+ * interrupts, on T6041 (checked against a J616C ADT). The CPUs differ: two
+ * clusters of six P cores instead of five. Binned parts leave cores out of
+ * the ADT (the 14-core part has no cpu9 and no cpu15); the boot loader
+ * matches the DT's CPU nodes to the ADT's in order and disables those it
+ * does not find, so t6040.dtsi adds the sixth core of each cluster in place.
+ *
+ * The main PMIC is a Chapel at SPMI address 0xb (ADT nub-spmi0
+ * spmi-chapelL1-b), not T6040's Abbey at 0xe; its nvmem cells sit at the
+ * same offsets.
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+#define T6041_SIX_CORE_P_CLUSTERS
+#include "t6040.dtsi"
+
+/ {
+	cpus {
+		cpu-map {
+			cluster1 {
+				core5 {
+					cpu = <&cpu_p05>;
+				};
+			};
+
+			cluster2 {
+				core5 {
+					cpu = <&cpu_p15>;
+				};
+			};
+		};
+	};
+};
+
+&nub_spmi0 {
+	/delete-node/ pmic@e;
+
+	pmic@b {
+		compatible = "apple,chapel-pmic", "apple,spmi-nvmem";
+		reg = <0xb SPMI_USID>;
+
+		/* ADT pmu,chapel info-rtc_alarm_*: the Abbey layout at 0x2000 */
+		pmu_rtc: rtc {
+			compatible = "apple,t6041-pmu-rtc";
+			interrupt-parent = <&nub_spmi0>;
+			interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+			nvmem-cells = <&rtc_offset>;
+			nvmem-cell-names = "rtc_offset";
+			wakeup-source;
+		};
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			rtc_offset: rtc-offset@2100 {
+				reg = <0x2100 0x6>;
+			};
+
+			boot_stage: boot-stage@f801 {
+				reg = <0xf801 0x1>;
+			};
+
+			boot_error_count: boot-error-count@f802,0 {
+				reg = <0xf802 0x1>;
+				bits = <0 4>;
+			};
+
+			panic_count: panic-count@f802,4 {
+				reg = <0xf802 0x1>;
+				bits = <4 4>;
+			};
+
+			shutdown_flag: shutdown-flag@f80f,3 {
+				reg = <0xf80f 0x1>;
+				bits = <3 1>;
+			};
+		};
+	};
+};
+
+/*
+ * Four cache planes per AMCC, eight AMCCs on the full part and six on the
+ * binned one (ADT amcc-enable-mask 0x3f). List the six every T6041 has.
+ */
+&mcc {
+	reg = <0x2 0x20000000 0x0 0x4000>,
+	      <0x2 0x20040000 0x0 0x4000>,
+	      <0x2 0x20080000 0x0 0x4000>,
+	      <0x2 0x200c0000 0x0 0x4000>,
+	      <0x2 0x22000000 0x0 0x4000>,
+	      <0x2 0x22040000 0x0 0x4000>,
+	      <0x2 0x22080000 0x0 0x4000>,
+	      <0x2 0x220c0000 0x0 0x4000>,
+	      <0x2 0x24000000 0x0 0x4000>,
+	      <0x2 0x24040000 0x0 0x4000>,
+	      <0x2 0x24080000 0x0 0x4000>,
+	      <0x2 0x240c0000 0x0 0x4000>,
+	      <0x2 0x26000000 0x0 0x4000>,
+	      <0x2 0x26040000 0x0 0x4000>,
+	      <0x2 0x26080000 0x0 0x4000>,
+	      <0x2 0x260c0000 0x0 0x4000>,
+	      <0x2 0x28000000 0x0 0x4000>,
+	      <0x2 0x28040000 0x0 0x4000>,
+	      <0x2 0x28080000 0x0 0x4000>,
+	      <0x2 0x280c0000 0x0 0x4000>,
+	      <0x2 0x2a000000 0x0 0x4000>,
+	      <0x2 0x2a040000 0x0 0x4000>,
+	      <0x2 0x2a080000 0x0 0x4000>,
+	      <0x2 0x2a0c0000 0x0 0x4000>;
+};