[RyanTheTide]

J616s dock HDMI over USB-C pin D

Based on the J616s batch1 kernel at d34a031e, which includes the #451/#515
external display fabric and the #506 nonoverlapping DT parity pieces. The
published batch1 head e1a25b5e adds only a host selftest fixture fix, so
the runtime source is the same before this PHY patch. The
orchestrator's J616s run with m1n1 #56 showed dcpext0/1 handoff and the
display gate working, built-in HDMI-A-1 enumerating, eDP/GUI intact, and no
WARN or DART faults. The dock negotiated DP pin assignment D but no DP
connector appeared: the T6040 PHY rejected D.

This patch adds the two-lane D mode to the existing T6040 PHY. It latches the
pin assignment before DCP claims the Type-C route, reports two DP lanes to
the DPTX trainer, keeps USB3's coprocessor and PIPE on the other pair, selects
the orientation-specific ATC lane group and restores the ordinary USB3
teardown once DCP releases DP. The two-lane link register tables come from
Dj's public GPL-2.0-only-or-MIT T6050 combo PHY series (#480), with credit
in the new header. The existing C/E four-lane and fixed HDMI paths stay on
their prior sequences. No DT edit or runtime parameter is needed.

The measurement candidate pairs this kernel with
stage2-dcpext-1bf9ec57-r2 (m1n1 #56) for both external DCP memory
handoffs and the GPU calibration handoff. The three DCP TEXT reservations
still refer to one validated immutable TEXT image; their duplicate
reservation warnings are a separate cleanup.

Ryan's dock acceptance is an EDID-named 1920x1080@180 Hz display with
colours matching Neo. Batch1 already has the guarded 414.09 MHz RGB8,
full-range sRGB mode (dcp-180hz-policy.h), requiring two trained HBR3
lanes. Its 9.93816 Gbit/s payload does not fit two HBR2 lanes (8.64
Gbit/s) and does fit two HBR3 lanes (12.96 Gbit/s). The parser and common
scanout already select external SDR RGB/full range, BGRA pixels, sRGB source
tagging and the CRTC colour matrix. Hardware must confirm actual EDID name,
mode/OSD, configured rate and lanes, and colour test pattern before this
is accepted.

Qualification

• T6040 PHY object compile: pass with batch1 release config.
• Full WERROR Image/modules/DTBs: pass with the unchanged batch1 config at
  final head 31340abccfcc3f7f9669fa327d8771a3cadd4f3f.
• J616s CHECK_DTBS=y and T6040 ATC binding check: pass. A broader
  Type-C routes binding run reports seven pre-existing T6020 example
  diagnostics; the failure log is preserved in the task report.
• Offline tether candidate:
  candidates/boot-7.3.0-aurora-j616s-dp2-u2, paired with
  stage2-dcpext-1bf9ec57-r2; SHA256SUMS, MANIFEST.sha256 and aligned
  current-GPT init append verify. Its boot plan uses --extra user4k=on.
• Hardware: pending controller-approved J616s tether run. Dock HDMI must
  negotiate D, enumerate, show EDID name, mode set 1080p180 visibly with
  HBR3 x2 and correct full-range colour, and retain USB3/Ethernet. Also
  check direct USB-C C/E or D, built-in HDMI, GPU calibration, eDP/GUI and
  zero WARN/DART faults. The candidate's MEASURE.md lists evidence and
  rollback steps.

This is a draft until the J616s measurement agent returns link training,
hotplug and regression evidence. Do not infer a dock pass from offline checks.
The exact source and candidate hashes have also been handed to t-3369 for
its batch2 tip build.

[RyanTheTide]

Landed in integration/aurora through #533 (J616s consolidation, 2026-10-28).