J616s (M4 Pro): external displays (Type-C through the display fabric, HDMI and USB-C DisplayPort behind the T6041 display gate) and the third loaded GPU image

Documentation/devicetree/bindings/display/apple,dcp.yaml

@@ -33,6 +33,7 @@ properties:
               - apple,t8112-dcpext
               - apple,t6000-dcpext
               - apple,t6020-dcpext
+              - apple,t6041-dcpext
           - const: apple,dcpext
       - items:
           - const: apple,t8140-dcpext
@@ -213,6 +214,23 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: Display coprocessor index on multi-DCP systems.
 
+  apple,typec-hybrid-first:
+    type: boolean
+    description:
+      A hybrid pipeline (a fixed output plus Type-C routes) is planned for a
+      Type-C port before the other pipelines, while its fixed output has no
+      sink, instead of being kept back for that output. Set where this
+      pipeline is the only one that can be the primary of a display wider than
+      one pipe.
+
+  apple,dcp-endpoint:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The display endpoint this coprocessor is to its firmware (its display
+      index), by which two external pipes name each other when a display
+      wider than one pipe is driven by two of them. 0 is the internal
+      display.
+
   apple,dptx-phy:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: DisplayPort transmitter PHY selector.

Documentation/devicetree/bindings/power/apple,t8140-pmp-report.yaml

@@ -93,6 +93,13 @@ patternProperties:
           holds this entry's device ID, instead of by reg. Only valid on a
           report whose PMP the host starts.
 
+      apple,irq-safe:
+        type: boolean
+        description:
+          The entry is the parent of IRQ-safe PMGR power states and is
+          switched with interrupts disabled. Setting the state takes a
+          spinlock and polls the acknowledgment atomically.
+
     required:
       - compatible
       - reg

arch/arm64/boot/dts/apple/t6040-j616s-extdisp-hdmi.dtsi

@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * The fixed HDMI path of t6040-j616s-extdisp.dtsi (dcpext0 -> atc3 crossbar
+ * -> atcphy3 -> DP-to-HDMI converter) with every node left DISABLED. The
+ * nodes must not be enabled at boot in the device tree: powering the DISPEXT
+ * chain without the PMP acknowledgement hangs the machine before root. The
+ * enable gate (drivers/soc/apple/t6041-display-gate.c) switches them on in
+ * order once the PMP is bound.
+ *
+ * dispext0's DART is not in the display node's iommus: the gate appends it
+ * when it enables the chain, so the internal display's DART domain stays as
+ * it is without the external displays.
+ */
+
+/*
+ * DISPEXT0 may only be powered once the PMP has acknowledged it in its
+ * device-state table (SOC-DEV-PS-REQ/ACK, PTD entries 480/488 on T6041): the
+ * soc-device record of DISPEXT0 has ID 18 (ADT iop-pmp-nub soc-device, ack
+ * flag set), so its request bit is 17. Without it, enabling the DISPEXT0 PMGR
+ * chain hung the machine before root.
+ * Same contract as the T6030 PMP device-state provider of
+ * aurora-silicon/linux#358, through the existing pmp-report entries here.
+ */
+&pmp_report {
+	pmp_dispext0: report@11 {
+		compatible = "apple,t6041-pmp-v2-report-entry",
+			     "apple,t6000-pmp-v2-report-entry";
+		reg = <0x11>;
+		label = "pmp-dispext0";
+		#power-domain-cells = <0>;
+		/* parent of the IRQ-safe PMGR chain */
+		apple,irq-safe;
+		status = "disabled";
+	};
+};
+
+&ps_dispext0_sys {
+	power-domains = <&pmp_dispext0>;
+	status = "disabled";
+};
+
+&ps_dispext0_fe {
+	status = "disabled";
+};
+
+&ps_dispext0_cpu {
+	/*
+	 * NEVER enable: the ADT marks DISPEXT0_CPU no_ps (no PMGR power-state
+	 * register, like the internal DISP_CPU). Its probe reads offset 0x350,
+	 * and that read resets the SoC. DCPEXT0's own power gate (ADT power-gates 431) is the
+	 * virtual DISPEXT0-CPU-V; the last real register of the chain is FE.
+	 */
+	/delete-property/ apple,always-on;
+	status = "disabled";
+};
+
+&ps_atc3_common {
+	status = "disabled";
+};
+
+&ps_atc3_common_dp {
+	status = "disabled";
+};
+
+&ps_atc3_usb_aon {
+	status = "disabled";
+};
+
+&ps_atc3_phymxwrap {
+	status = "disabled";
+};
+
+&pmgr_mini {
+	/* ADT ATC3_USB: +0x148, parents ATC3_COMMON and ATC3_USB_AON; the crossbar's domain as on T6030 */
+	ps_atc3_usb: power-controller@148 {
+		compatible = "apple,t6041-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate";
+		reg = <0x148 4>;
+		#power-domain-cells = <0>;
+		#reset-cells = <0>;
+		label = "atc3_usb";
+		power-domains = <&ps_atc3_common>, <&ps_atc3_usb_aon>;
+		status = "disabled";
+	};
+};
+
+&pinctrl_aop {
+	status = "disabled";
+};
+
+&dcpext0_dart {
+	/* in the DISPEXT0 block: powered (after the PMP request) before probing */
+	power-domains = <&ps_dispext0_fe>;
+	status = "disabled";
+};
+
+&dispext0_dart {
+	/* in the DISPEXT0 block: powered (after the PMP request) before probing */
+	power-domains = <&ps_dispext0_fe>;
+	status = "disabled";
+};
+
+&dcpext0_mbox {
+	power-domains = <&ps_dispext0_fe>;
+	status = "disabled";
+};
+
+&dcpext0 {
+	power-domains = <&ps_dispext0_fe>;
+	/*
+	 * The IOMFB surface layout of the internal DCP;
+	 * without apple,iomfb-surfaces apple-dcp's probe fails with -EINVAL.
+	 */
+	apple,iomfb-surfaces = <1 1 0 0>;
+	status = "disabled";
+};
+
+&atcphy3_mbox {
+	status = "disabled";
+};
+
+&atcphy3_xbar {
+	power-domains = <&ps_atc3_usb>;
+	status = "disabled";
+};
+
+/*
+ * atcphy3 apply_tunables tables (aciophy_phy_init mode 3), from this machine's ADT /arm-io/atc-phy3
+ * (privateartifacts/omarchy-m4-unit/adt.bin): AXI2AF converted entry by entry; every other table is
+ * byte-identical to atc-phy0 in the ADT, so the atcphy0 values of t6040-j616s-usb3.dtsi are reused
+ * (AUS40CMN_SHM differs: 0x50). Only the first six (axi2af..lane1) are applied in DP mode.
+ */
+&atcphy3 {
+	/* ATC3 ADT tunable_ATC0AXI2AF (port-specific), entries <offset mask value> */
+	apple,tunable-axi2af =
+		<0x0 0x800000ff 0x80000025>,
+		<0x4 0x80ff00ff 0x80250003>,
+		<0x8 0x80ff00ff 0x80250003>,
+		<0xc 0x80ff00ff 0x80250005>,
+		<0x10 0x80ff00ff 0x80250003>,
+		<0x14 0x80ff00ff 0x80250003>,
+		<0x18 0x80ff00ff 0x80250003>,
+		<0x1c 0x80ff00ff 0x80250003>,
+		<0x20 0x800000ff 0x8000001e>,
+		<0x24 0x800000ff 0x8000004a>,
+		<0x28 0x80ff00ff 0x804a0006>,
+		<0x2c 0x80ff00ff 0x804a0006>,
+		<0x30 0x80ff00ff 0x804a0006>,
+		<0x34 0x80ff00ff 0x804a0006>,
+		<0x38 0x80ff00ff 0x804a0006>,
+		<0x3c 0x80ff00ff 0x804a0006>,
+		<0x40 0x800000ff 0x8000001e>,
+		<0x44 0x800000ff 0x8000001e>,
+		<0x48 0x800000ff 0x8000001e>,
+		<0x100 0x000000ff 0x000000ff>,
+		<0x108 0xffff0006 0x00100000>,
+		<0x304 0x3f3f0000 0x04040000>,
+		<0x308 0x000fffff 0x00001681>,
+		<0x30c 0x000fffff 0x00001680>,
+		<0x310 0x70000fff 0x000001e0>,
+		<0x314 0xf0000fff 0x800001e0>,
+		<0x318 0x70000fff 0x000001e0>,
+		<0x31c 0xf0000fff 0x800001e0>,
+		<0x320 0x70000fff 0x000005a0>,
+		<0x324 0xf0000fff 0x800005a0>,
+		<0x328 0x70000fff 0x000005a0>,
+		<0x32c 0xf0000fff 0x800005a0>,
+		<0x330 0x70000fff 0x000005a0>,
+		<0x334 0xf0000fff 0x800005a0>,
+		<0x338 0x70000fff 0x000005a0>,
+		<0x33c 0x70000fff 0x000005a0>,
+		<0x340 0x70000fff 0x000005a0>,
+		<0x344 0x70000fff 0x000005a0>,
+		<0x348 0x70000fff 0x000005a0>,
+		<0x34c 0x70000fff 0x000005a0>,
+		<0x350 0x70000fff 0x000005a0>,
+		<0x358 0xffffffff 0x0000ffff>,
+		<0x35c 0xffffffff 0x0000ffff>,
+		<0x408 0xffff0020 0x00210020>,
+		<0x40c 0x000fffff 0x00001681>,
+		<0x410 0x000fffff 0x00001680>,
+		<0x414 0x70000fff 0x000001e0>,
+		<0x418 0x70000fff 0x000001e0>,
+		<0x41c 0x70000fff 0x000001e0>,
+		<0x420 0x70000fff 0x000001e0>,
+		<0x424 0x70000fff 0x000005a0>,
+		<0x428 0x70000fff 0x000005a0>,
+		<0x42c 0x70000fff 0x000005a0>,
+		<0x430 0x70000fff 0x000005a0>,
+		<0x434 0x70000fff 0x000005a0>,
+		<0x438 0x70000fff 0x000005a0>,
+		<0x43c 0x70000fff 0x000005a0>,
+		<0x440 0x70000fff 0x000005a0>,
+		<0x444 0x70000fff 0x000005a0>,
+		<0x448 0x70000fff 0x000005a0>,
+		<0x44c 0x70000fff 0x000005a0>,
+		<0x450 0x70000fff 0x000005a0>,
+		<0x454 0x70000fff 0x000005a0>,
+		<0x948 0x07ff07ff 0x00280000>,
+		<0xa48 0x07ff07ff 0x00400040>,
+		<0xb48 0x07ff07ff 0x00b8010e>,
+		<0xc48 0x07ff07ff 0x00400020>,
+		<0xd48 0x07ff07ff 0x008a008a>,
+		<0x1000 0xffffffff 0x7fffffff>,
+		<0x4008 0x00000001 0x00000001>,
+		<0x400c 0x00000001 0x00000001>,
+		<0x4014 0x00000001 0x00000001>,
+		<0x4018 0x00000001 0x00000000>,
+		<0x401c 0x00000001 0x00000001>;
+	/* the remaining tables equal atc-phy0 in the ADT, except AUS40CMN_SHM (0x50) */
+	apple,tunable-fabric =
+		<0x4 0x003f003f 0x00200020>,
+		<0xc 0x000000f1 0x000000a1>,
+		<0x10 0x0000801f 0x00000004>,
+		<0x18 0x003f003f 0x00200020>,
+		<0x20 0x000000f1 0x000000a1>,
+		<0x24 0x0000801f 0x00000004>,
+		<0x2c 0x00ff00ff 0x00960096>,
+		<0x34 0x000000f1 0x00000071>,
+		<0x38 0x0000801f 0x00000004>,
+		<0x40 0x0000003f 0x00000020>,
+		<0x48 0x0000801f 0x00000004>,
+		<0x50 0x007f007f 0x00450045>,
+		<0x58 0x0000801f 0x00000004>,
+		<0x60 0x0000003f 0x00000020>,
+		<0x68 0x0000801f 0x00000004>,
+		<0x70 0x00000001 0x00000001>,
+		<0x74 0x0000801f 0x00000004>,
+		<0x7c 0x007f007f 0x00400040>,
+		<0x80 0x000000f1 0x00000011>,
+		<0x84 0x00000001 0x00000001>,
+		<0x88 0x00000001 0x00000001>,
+		<0x8c 0x0000801f 0x00000004>,
+		<0x94 0x001f001f 0x00100010>,
+		<0x98 0x000000f1 0x00000011>,
+		<0x9c 0x0000801f 0x00000004>,
+		<0xa4 0x000000ff 0x000000e0>,
+		<0xa8 0x0000801f 0x00000004>,
+		<0xb0 0x0000003f 0x00000020>,
+		<0xb8 0x0000801f 0x00000004>,
+		<0xc0 0x0000003f 0x00000020>,
+		<0xc8 0x0000801f 0x00000004>,
+		<0xd0 0x001f001f 0x00100010>,
+		<0xd8 0x00000001 0x00000001>,
+		<0xdc 0x00000001 0x00000001>,
+		<0xe0 0x0000801f 0x00000004>,
+		<0xe8 0x0000000f 0x00000008>,
+		<0xec 0x0000801f 0x00000004>,
+		<0xf4 0xffffffff 0x01010101>,
+		<0xf8 0x0000801f 0x00000004>,
+		<0x100 0x00000001 0x00000001>,
+		<0x104 0x00000001 0x00000001>,
+		<0x108 0x0000801f 0x00000004>,
+		<0x110 0x0000801f 0x00000004>,
+		<0x118 0x0000801f 0x00000004>,
+		<0x120 0x00000001 0x00000001>,
+		<0x124 0x00000001 0x00000001>,
+		<0x128 0x0000801f 0x00000004>,
+		<0x130 0xffffffff 0x01010101>,
+		<0x134 0x0000801f 0x00000004>,
+		<0x13c 0x00000001 0x00000001>,
+		<0x140 0x00000001 0x00000001>,
+		<0x144 0x0000801f 0x00000004>,
+		<0x14c 0x00000001 0x00000001>,
+		<0x150 0x00000001 0x00000001>,
+		<0x154 0x0000801f 0x00000004>,
+		<0x15c 0x0000801f 0x00000004>,
+		<0x164 0xffffffff 0x01010101>,
+		<0x168 0x0000ffff 0x00000101>,
+		<0x16c 0x0000801f 0x00000004>,
+		<0x174 0x00000001 0x00000001>,
+		<0x178 0x00000001 0x00000001>,
+		<0x17c 0x0000801f 0x00000004>,
+		<0x184 0x00000001 0x00000001>,
+		<0x188 0x00000001 0x00000001>,
+		<0x18c 0x0000801f 0x00000004>;
+	apple,tunable-common-cfg =
+		<0x8 0x00000001 0x00000001>;
+	apple,tunable-axi2af-lioa =
+		<0x28 0x0000fe2f 0x00000000>,
+		<0x2c 0x00000007 0x00000000>,
+		<0x30 0x0000007f 0x00000000>,
+		<0x34 0x000000ff 0x00000000>,
+		<0x58 0x0000010b 0x00000000>;
+	apple,tunable-lane0 =
+		<0xd094 0x00080000 0x00080000>,
+		<0xd098 0x00080000 0x00080000>,
+		<0xd0a4 0x00800000 0x00800000>,
+		<0xd0a8 0x00200000 0x00200000>;
+	apple,tunable-lane1 =
+		<0x1d094 0x00080000 0x00080000>,
+		<0x1d098 0x00080000 0x00080000>,
+		<0x1d0a4 0x00800000 0x00800000>,
+		<0x1d0a8 0x00200000 0x00200000>;
+	apple,tunable-aus40cmn-shm =
+		<0xa04 0x0000007c 0x00000050>;
+	apple,tunable-auspll =
+		<0x3224 0x00000c00 0x00000800>,
+		<0x3230 0x0000001f 0x0000000f>,
+		<0x3240 0x07d8007f 0x04000059>,
+		<0x32b0 0x0b800000 0x01800000>,
+		<0x32e8 0x00060001 0x00040001>,
+		<0x3338 0x0f800000 0x07800000>;
+	apple,tunable-cio4pll =
+		<0x3a30 0x0000001f 0x0000000f>,
+		<0x3a4c 0x0000fe7f 0x0000501e>,
+		<0x3ab0 0x00700000 0x00300000>,
+		<0x3ae8 0x00060000 0x00020000>;
+};