[petrskuta]

On the desktop 26.6 firmware, SET_TILED_DISPLAY_HINTS goes to the
dual-pipe allocation (dcp_peer_hints_26_6()) and returns from there.
That path never records the tile the port carries, so
dptxport[0].tile_hint stays false and a tiled display behind a
Thunderbolt tunnel can never take its second tile on dpin1
(dcp_tb_split_*): the split waits for the hint, then gives up.

The Studio Display on Thunderbolt 3 is such a sink: two 2560x2880 tiles,
5120 wide, which is under DCP_DESKTOP_PIPE_MAX_WIDTH, so no peer pipe is
allocated either. Split the recording out of
dptxport_call_set_tiled_display_hint() and also run it for a tunnel on
26.6, before the allocation. A J614s now logs

DPTXPort: port 0 carries tile (0,0) of a 2x1 tiled 5120x2880 display

The allocation reply is unchanged, and so is every other firmware and
DP alt mode route.

Testing

On a MacBook Pro 14" M4 Pro (apple,j614s), os-fw 26.6.2, Studio Display (2022) on Thunderbolt 3, with the trial commits from #1589.

• Before: no tile line; dptxport[0].tile_hint stayed false.
• After: DPTXPort: port 0 carries tile (0,0) of a 2x1 tiled 5120x2880 display.
• dpin1 doesn't join yet: the display's second DP OUT (1:11) raises no HPD while the first tile has no video (see M4 Pro/Max (T6040/T6041): Thunderbolt displays need a DP tunnel pixel clock in the T6040 PHY #1589 and thunderbolt: share an Apple host link between DP tunnels that come up together omacom/linux-aurora#154).
• Compile-tested on aa68b3c81830 (W=1, no new warnings).

🤖 Generated with Claude Code

[DjDeveloperr]

Approve: the tile hint is recorded on the 26.6 desktop path only for a tunnel (dptx_tunnel && DCP_FIRMWARE_V_26_6_DESKTOP); the allocation reply and every other firmware path are unchanged. Merging after a fresh CI run on the current base (dptxep.c changed since the last run).