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arm64: dts: apple: t6050-j714s: Add the left-front port's USB4 router - #1791
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The left-front USB-C port (ATC1) had only its PD controller, USB 2/3 and DisplayPort alt mode described. A USB4 device there got a PD contract and the PHY switched to USB4, but with no router nothing trained the link, so there was no tunnel and no fallback. Describe ATC1's USB4/Thunderbolt router (acio1, its CPU mailbox, DART and NHI) and its PCIe tunnel (apciec1 and its DART) as the right port's, with the J714sAP ADT's addresses, interrupts, tunables and host DROM, and link hpm1's connector to the router. The router, DART and tunnel tunables equal ATC2's. The PHY's CIO RX_TOP lane tunables differ from ATC2's and are this port's. The router's LSTX pin, AOP GPIO 79, is exposed next to ATC2's 81. The shared inventory's disabled apciec1 DART now stays out of J714s, as it does for J716c, which describes the same nodes. Signed-off-by: Diljit Singh <hey@djdev.me>
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J714s (MacBook Pro 14" M5 Pro): describe the left-front USB-C port's (ATC1) USB4/Thunderbolt router and its PCIe tunnel, as the right port (ATC2) already is.
Before this, ATC1 had only its PD controller, USB 2/3 and DisplayPort alt mode. A USB4 device on it got a PD contract and the PHY switched to "USB3 PIPE on the USB4 tunnel", but with no router nothing trained the link. There was no tunnel, no USB 2/3 fallback and no device.
What changes
t6050-j714s-left-usb4.dtsi: acio1 (router, CPU mailbox, DART, NHI) and pcie-tunnel-1 (apciec1 and its DART), plus the ATC1 power domains. Addresses, interrupts, tunables and the host DROM come from the J714sAP ADT (/arm-io/acio1, acio-cpu1, dart-acio1, apciec1, dart-apciec1, atc-phy1).t6050-j716c-left-usb4.dtsi) and the right port's (t6050-max-atc2.dtsi).t6050-peripherals.dtsi: the inventory's disabled apciec1 DART is left out of J714s, as it already is for J716c, because the tunnel now defines it.No driver changes. Related: #1579 adds disabled acio0/1/3 routers to shared files. It doesn't add the PCIe tunnels, and this PR doesn't depend on it.
Tested on J714s (one lab boot, 2026-11-13). Default kernel 7.3.0-m5-intg6 (integration/aurora eb6b241) with this DT on top of intg6's DT; the dtsi is byte-identical to this PR's. Attached was a Satechi USB4 NVMe SSD Pro Enclosure (ASMedia ASM2464PD) holding the owner's data, so the check was read-only by design.
Not tested
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