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arm64, KVM, irqchip/apple-aic: KVM guests on the J813 (M5 MacBook Air) at EL2 #1728

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Merged
DjDeveloperr merged 3 commits into from
Nov 12, 2026
Merged

arm64, KVM, irqchip/apple-aic: KVM guests on the J813 (M5 MacBook Air) at EL2 #1728

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a63554b
arm64: errata: treat the T8142 vGIC SEIS as broken, like T6040 and T8140
sithglan Nov 12, 2026
d224f77
KVM: arm64: Fix up ID_AA64PFR1_EL1.MTE_frac only for a VM with MTE
sithglan Nov 12, 2026
14beccb
irqchip/apple-aic: Mask T8142 guest timers through VM_TMR_FIQ_ENA_EL2…
sithglan Nov 12, 2026
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2 changes: 2 additions & 0 deletions arch/arm64/kernel/cpu_errata.c
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Original file line number Diff line number Diff line change
Expand Up @@ -316,6 +316,8 @@ static const struct midr_range apple_broken_seis_cpus[] = {
MIDR_ALL_VERSIONS(MIDR_APPLE_T6040_P),
MIDR_ALL_VERSIONS(MIDR_APPLE_TAHITI_E),
MIDR_ALL_VERSIONS(MIDR_APPLE_TAHITI_P),
MIDR_ALL_VERSIONS(MIDR_APPLE_T8142_E),
MIDR_ALL_VERSIONS(MIDR_APPLE_T8142_P),
{},
};

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7 changes: 6 additions & 1 deletion arch/arm64/kvm/sys_regs.c
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Expand Up @@ -2535,9 +2535,14 @@ static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
* ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid
* incorrectly claiming hardware support for MTE_ASYNC in the
* guest.
*
* Only a VM with MTE sees MTE_frac. Without MTE both fields read
* as 0 and the 0 written back must stay 0, or the value no longer
* matches the one KVM itself provided.
*/

if (mte == ID_AA64PFR1_EL1_MTE_MTE2 &&
if (kvm_has_mte(vcpu->kvm) &&
mte == ID_AA64PFR1_EL1_MTE_MTE2 &&
hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI &&
user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) {
user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK;
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12 changes: 12 additions & 0 deletions drivers/irqchip/irq-apple-aic.c
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Expand Up @@ -1286,6 +1286,18 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p

irqc->info = *(struct aic_info *)match->data;

/*
* The VM_TMR_FIQ_ENA_EL2 write that traps on T8142 was seen under
* SPTM. A loader that runs the OS at EL2 in a CTXR execute window
* starts no SPTM and says so with this property, and there the
* register takes writes. Masking through the EL02 controls instead
* sets IMASK in the guest's own timer, which KVM then keeps as
* guest state: the guest gets no timer interrupt again.
*/
if (irqc->info.vm_timer_fiq_readonly && is_kernel_in_hyp_mode() &&
of_property_present(of_chosen, "aurora,ctxr-exec-window"))
irqc->info.vm_timer_fiq_readonly = false;

aic_irqc = irqc;

switch (irqc->info.version) {
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