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The J613 ADT gives SPI2 clock ID 0x198 a 24 MHz boot frequency. On hardware, divider 25 produces 0.96 MHz: six 29184-byte frames take 243.2 ms and overrun the 229 ms receive deadline. Use the existing 24 MHz reference clock so an 8 MHz request selects divider 3. Leave SPI1 unchanged pending evidence for that controller. Signed-off-by: Satya Benson <satya@benson.earth>
The divider rounds up, so a requested transfer rate can exceed the achieved rate even when the input clock is described correctly. Record the effective speed after clamping the divider and use it for the IRQ transfer deadline and the polling decision. Add a host test extracting the production preparation function and timeout expression. Cover exact and rounded divisors, the divider limit and the polling threshold with address and undefined-behavior sanitizers. Signed-off-by: Satya Benson <satya@benson.earth>
The J613 boot clock table also describes SPI4 clock ID 0x19a as 24 MHz. Use clkref for this unclaimed controller; the QSPI clock ID 0x188 is 200 MHz and remains unchanged. Signed-off-by: Satya Benson <satya@benson.earth>
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Claude Fable 5.2 on @satchlj's behalf Hardware confirmation of the device-tree part, with an unpatched driver (2026-11-11, J613 M3 MacBook Air).
Not observed: frame duration and the programmed clock divider. This kernel logs neither, so the expected ~29 ms frames and divider 3 are not confirmed by these records. The driver part of this PR was not run here. |
RyanTheTide
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The effective-rate accounting is right, and the J613 frame timing confirms the 24 MHz input. One small hardening: if clk_get_rate() ever returns 0, cr is 0 and the new effective_speed_hz line divides by zero; clamping cr to at least 1 would avoid that. We will run it on our SPI keyboard and Touch ID machines before merging.
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Interim results. Kernel: integration e661192 plus this PR and the others in this round, one-shot.
The M2 (SPI keyboard) run is still queued. The |
If clk_get_rate() returns zero, the calculated divider is zero and computing effective_speed_hz divides by zero. Clamp the divider to at least one before programming it and calculating the effective speed, as suggested by RyanTheTide in review. Non-zero clock rates retain their existing behavior. Signed-off-by: Satya Benson <satya@benson.earth>
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GPT-6.1 Sol on @satchlj's behalf Pushed b876103 as one signed-off, fast-forward commit, addressing RyanTheTide's review. In Checks:
This commit has NOT been booted on hardware. The J613 is away until Friday 2026-11-13 afternoon US Eastern. The change does not alter behaviour for a non-zero clock rate. |
Claude Fable 5.2 on @satchlj's behalf
Fixes Touch ID matching on J613 (M3 MacBook Air, T8122), which failed with SPI receive timeouts while reading fingerprint frames. This is the remaining failure reported on #1491 (0 matches in 6 attempts); #1491 fixed the transmit-only case and did not touch this path.
Cause. The T8122 device tree gives SPI2 (the fingerprint sensor's bus,
spi@2a1108000) and SPI4 (spi@2a1110000) a 200 MHz input clock. Their real input is the 24 MHz reference. For an 8 MHz device the driver therefore programmed divider 25 and the bus ran at 0.96 MHz. A 29,184-byte frame took 243.2 ms against a 229 ms timeout.Evidence for 24 MHz
Commits
arm64: dts: apple: t8122: Fix the fingerprint SPI input clock: SPI2 references the 24 MHz clock.spi: apple: Account for the programmed clock in receive timeouts: the timeout and the polling decision use the rate actually achieved after divider rounding, not the requested rate, so a rounded divider cannot reproduce this failure. Adds a host test (tools/spi/apple-spi-clock-test.py) that rejects the original driver.arm64: dts: apple: t8122: Correct the SPI4 reference clock: same correction for SPI4.Tested on hardware (J613, exact head f1c9d85)
Kernel
7.3.0-aurora73-exact-1111-spi-D-ARCH, which is integration plus the then-open J613 PR heads plus these three commits and one transfer-metadata debug line, booted with a one-shot Stage 2 carrying the corrected device tree (the running device tree on this machine comes from the boot loader, so the dts change only takes effect through a rebuilt Stage 2)./clock-ref, 24 MHz.clk=24000000 div=3on every transfer.fprintd-verify, @satchlj's enrolled finger). Seven earlier verification windows expired with no finger on the sensor and attempted no frame transfer.Offline
Not tested
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