[DjDeveloperr]

Adds the MacBook Pro 14-inch (M5 Pro, J714s) SD card reader, a GL9755 on internal PCIe port 1 (ADT pci-bridge1/pcie-sdreader). The boot loader leaves that port down, so the kernel cold-trains it with #1182's T6050 path, the way the J716s N1 is trained. Two commits:

1. PCI: apple: T6050: don't restart a shared PHY the boot loader started.
   • Problem: before training, the cold train checks whether the shared PHY runs, but only recognised the state its own start leaves. Aura starts that PHY in macOS's post-iBoot order when it trains the N1's port, which leaves status bit 4 set and the RC ready. So the kernel tried to start the PHY again under port 0's live link. On J714s it stopped only because the phy-common window was missing.
   • Fix: take aura's state as running too. That is the check aura itself makes before training a port (stage_s/stage_b in src/pcie_t6050.c). 13 lines.
2. arm64: dts: apple: t6050-j714s: Add the SD card reader.
   • Port 1: its registers, interrupt (1531) and link tunables from pci-bridge1.
   • Shared PHY: its window (phy-shared, ADT reg[3]), which the train reads.
   • Power and reset: the reader's power as SMC pcIO output 0, from the ADT's function-sd_pwr_en template pKW8('pcIO', 0x0, 0x190000). PERST# is GPIO 81, which the pin controller now exposes; pin 112 stays reserved.
   • DART: dart-apcie1, stream 1, with apple,manual-availability. It is new in t6050-die0.dtsi, disabled there, so other T6050 boards gain only a disabled node.
   • Card detect and write protect: cd-inverted and wp-inverted on the reader's node. Both lines are active high on this board (the ADT's polarity is 1). Without them a card in the slot is never detected.

Hardware validation on J714s:

• Test kernel: integration/aurora as of 11-10 + drm/asahi, drm/apple: M5 GPU and firmware-27 display on integration/aurora #1012 + drm/apple: send firmware 27 swap timestamps in the firmware's timebase #1404, the T6050 USB4 display stack, PCI: apple: train a T6050 root port the boot loader left down (J716s N1) #1182's twelve commits, and commit 1.
• DTB: this branch's J714s DTB plus the unit's GPU leakage words; otherwise identical to what this branch builds.
• Port 1: "port 1: trained by Linux, the boot loader left it down". The GL9755 [17a0:9755] enumerated at 5 GT/s x1 (the Gen2 the ADT's expected-link-speed asks for, and what macOS retrains to), sdhci-pci bound, and mmc0 registered with ADMA 64-bit.
• Card (run sd6, this head's DT): a 64 GB UHS-II SDXC card in the slot at boot was detected (mmc0: new UHS-II speed SDXC card) and its exFAT partition read back. Everything was read-only: the block devices were set read-only as they appeared, and the mount was read-only. A 512 MiB direct read ran at 16 MB/s, with no oops. Without the polarity properties (run sd5), the same card was never detected.
• Port 0: the N1 was adopted unchanged, with Wi-Fi up. A soft reboot of this kernel came back with Wi-Fi, and its shutdown was clean.
• Kernel log: no oops, no WARNING, no deferred devices.

Not tested: card writes, card hot-insertion, read speed against macOS (16 MB/s looks low for UHS-II), and SDR104 tuning. The ADT carries GL9755 SDR104 delay values (gl9755-sdr104-delay*) that this doesn't apply.

🤖 Generated with Claude Code

[DjDeveloperr]

Head e8a416c adds card detect: cd-inverted and wp-inverted on the GL9755's node. Both lines are active high on this board.

Hardware (J714s, run sd6, read-only):

• A 64 GB UHS-II SDXC card in the slot at boot was detected (mmc0: new UHS-II speed SDXC card at address 0001, mmcblk0 59.6 GiB).
• Its exFAT partition mounted read-only and listed its folders. The block devices were set read-only as they appeared, and nothing wrote to the card.
• A 512 MiB direct read ran at 16 MB/s.
• No oops.
• A soft reboot of the test kernel came back cleanly.

Without these properties (run sd5), the same card was never detected: the host stayed powered off.

Open: card writes, hot-insertion, and read speed against macOS. 16 MB/s looks low for UHS-II.