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t6041-j575c: HDMI through the LPDPTX PHY - #1565
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RyanTheTide
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Reviewed the three new commits: the PHY binding fallback, the J575c stage in the display gate (board-gated), and the HDMI dtsi with everything disabled until the hand-off. The test table covers cold boot, replug and the no-hand-off case. Approved once CI has run. A rebase onto current integration/aurora would drop the already-merged #1546 commits from this PR's view.
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@RyanTheTide Rebased onto integration/aurora (bf00add). The #1546 commits dropped out, so it's down to the three HDMI commits. There were no conflicts, and the HDMI stage still works with the independent-chains gate from #1551. Thanks! |
RyanTheTide
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Rebase checked: the three HDMI commits match the reviewed version and CI is green on all jobs. Approved.
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@7robertodantas #1599 just merged and edits the same comment at the end of t6041-j575c.dts, so this now conflicts there. Could you rebase onto integration/aurora? The HDMI commits themselves are approved as they are. |
The T6041's LPDPTX PHY (ADT lpdptx-phy0, "dptx-phy,t8132") has the T6050 PHY's two banks at the same offsets (a 0x4000 "core" bank and a 0x10000 "dptx" bank 0x40000 above it) and takes the same ADT PLL calibration (DCOCFG, DTCVREG, DTCCAL, DCDADJ, DLFCFG) and source select, so it falls back to apple,t6050-dptx-phy. Assisted-by: LLM Signed-off-by: Roberto Dantas <7robertodantas@gmail.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The M4 Max HDMI stage is the J616c's: ATC3's power domains and PHY in DP mode, the ATC3 crossbar, then dcpext0. On the J575c ATC3 is the fourth back USB-C port, and the HDMI port runs through the LPDPTX PHY instead. On the J575c, the HDMI stage enables the LPDPTX PHY's power domain, the AOP pin controller (the DP-to-HDMI converter's hotplug), the PHY and dcpext0's DARTs, mailbox and processor. Nothing changes on the J614c and J616c. Tested on a J575c with the next commit and the aura J575c handoff: the gate enables dcp@3a2e00000's chain and a monitor on the HDMI port shows the console. Assisted-by: LLM Signed-off-by: Roberto Dantas <7robertodantas@gmail.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The J575c's HDMI port runs from the display crossbar's output 4 through the LPDPTX PHY (ADT lpdptx-phy0) to an on-board DP-to-HDMI converter. The converter's pins are the J616c's (ADT dp2hdmi-gpio0: hotplug on AOP GPIO 0x24, power enables on SMC gP0f and gP1a). macOS drives this port from the internal DCP, which aura's Stage 1 puts to sleep on this board. The crossbar has no registers and the PHY's source select picks the engine, so dcpext0 (crossbar input 0) drives it here, as on the M2 Max Mac Studio (t6021-j475c.dts). Describe the PHY with the ADT's PLL calibration and its PMGR domain (DPTX_PHY, pmgr + 0x360), dcpext0's firmware memory placeholders, and dcpext0 as an HDMI-A output on that PHY. All of it is disabled: the boot loader fills dcpext0's memory and the display gate enables the chain. Tested on a J575c with the aura J575c handoff (aurora-silicon/aura#160) and a 2560x1440 monitor on HDMI: the console shows at 2560x1440@59 over four lanes, from a cold boot and after a replug, and together with a second monitor on typec1. With aura 1.0.0b8 the gate logs "display subsystem not enabled" and nothing else changes; with the tree before this commit, the HDMI stage finds no firmware memory and is skipped. Assisted-by: LLM Signed-off-by: Roberto Dantas <7robertodantas@gmail.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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@RyanTheTide Rebased onto integration/aurora (fdef45b). The only conflict was the trailing comment in t6041-j575c.dts; #1599's PMP block is kept as is, and the HDMI commits are otherwise unchanged. |
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aurora-silicon:integration/aurora
Written with an AI assistant (Claude) on @7robertodantas's behalf; every hardware step was run and checked on the owner's J575c.
HDMI on the J575c (Mac Studio M4 Max). Builds on #1546 (the J575c display and USB3 PR): only the last three commits are new here. Like #1546's display, it needs aurora-silicon/aura#160, which already hands over dcpext0 once the tree has its placeholders; aura needs no further change.
How HDMI is wired. From the ADT and a read-only
ioregcapture under macOS with only the HDMI monitor connected: display-crossbar0 (ufp-endpointsdispext0-3, scodec0;dfp-endpointsatc0-3, lpdptx-phy0) routes to output 4,lpdptx-phy0(dptx-phy,t8132), which feeds the on-board DP-to-HDMI converter (dp2hdmi-gpio0: hotplug on AOP GPIO 0x24, power enables on SMC gP0f and gP1a, the same pins as the J616c). macOS drives it from the internal DCP (crossbar source 15), 4 lanes. aura's b8 Stage 1 puts that DCP to sleep on this board, so here dcpext0 (source 0) drives the port, as the M2 Max Mac Studio's tree does with its dcpext0. The crossbar has no registers; the PHY's source select picks the engine (ADTsource-select-offset1).The change.
dt-bindings: phy: apple,dptx-phy:apple,t6041-dptx-phy, falling back toapple,t6050-dptx-phy. Same banks at the same offsets (core 0x4000, dptx 0x10000 at +0x40000) and the same ADT PLL calibration properties, so the T6050 code path drives it with no driver change.display-gate: on the J575c the HDMI stage enables the LPDPTX PHY's power domain, the AOP pin controller, the PHY, then dcpext0's chain, instead of the J616c's ATC3 chain (ATC3 is a USB-C port here, t6041-j575c: USB-C display on typec1, USB3 and the fourth back Type-C port #1546).t6041-j575c: the PHY with the ADT's PLL values (DCOCFG 4, DTCVREG 0xf, DTCCAL 2, DCDADJ 0x10, DLFCFG 3; RODCOROLEAKCOMP and FD0FD1SWAP are unset), its domain (ADT pmgr DPTX_PHY, pmgr + 0x360), dcpext0's text/data/heap placeholders, and dcpext0 as an HDMI-A output on the PHY. All disabled until the boot loader fills dcpext0's memory and the gate runs.Tested on a J575c (Stage 1 1.0.0b8, aura#160 as an ESP Stage 2 trial), integration/aurora 1943af8 plus #1546 and these commits as a linux-aurora build, a 2560x1440 monitor on HDMI:
display subsystem not enabled, external displays left off, boots as before/dcp@3a2e00000: no firmware memory, nothing enabled, typec1 display unchangedThe firmware asks for 4 lanes while the driver's count is still 0, which logs
set_active_lane_count: unexpected lane count:4 phy: 0once per link-up; the lanes are then configured and the link comes up.Checks: dt-validate (dtschema 2026.9) on the J575c DTB: 0 warnings at the base (#1546) and at the head; the binding passes dt-doc-validate, and the PHY node is validated against it (an unknown property on it is reported). checkpatch --strict: 0 errors.
Not done: audio over HDMI; the other two back USB-C ports' displays (dcpext2/3).
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