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arm64: dts: apple: t6050-j714s: Describe the GPU and panel handoff - #1435
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Describe what the boot loader's J714s display and GPU handoff needs, all of it disabled until the loader has checked the hardware and enables it: - the internal DCP's panel (the 14.2-inch 3024x1964 mini-LED panel; this ADT carries no dimensions), the display subsystem on DART disp0 SID 0, and the 1 TiB + 3 TiB window of ADT dart-dcp and dart-disp0; - the four external engines: dcpext0 without its Type-C route (J714s keeps that crossbar off), dcpext1-3 without clocks (ADT clock-ids is empty) and the dcpext/dispext DART windows from the ADT; - the M5 Pro GPU: the gpu alias, the six reservations the loader fills, the GFX and GFX1 mailboxes at the physical gfx-asc/gfx1-asc windows (ADT reg, interrupts 2797/2800 and 2801/2804), GPX and AFR always on (the ADT marks them critical) and sgx as apple,agx-g17s. This is the DT the M5 Pro's default SSD boot has run since 2026-11-09, from its kit and integration overlays, with one exception: those also carried apple,leakage-calibration-words. The words are the unit's own fuse values (they gate the driver's J714 controller defaults), so they can't be a board property; the loader has to supply them. Signed-off-by: Diljit Singh <hey@djdev.me>
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The J714s uses the G17S compatible, one sgx MMIO window, two firmware mailbox roles and six firmware memory regions. Describe that layout without imposing the older calibration ABI or a board operating-point table. Document the per-unit calibration handoff as a loader-supplied property. Signed-off-by: Diljit Singh <hey@djdev.me>
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Describe the M5 Pro J714s GPU, internal panel and DCP handoff using the current integration board nodes. The GPU has one sgx MMIO range, two firmware mailbox roles and six firmware memory regions; the binding now describes that G17S layout without imposing the older calibration ABI or an operating-point table. Per-unit leakage words remain a boot-loader handoff, never board data.
Validation: the in-tree J714s DT compiles; focused apple,agx schema validation reports no J714s GPU warnings, including validation of the local loader-calibrated payload. The YAML-only binding fix leaves both the compiled Image and in-tree DTB hashes unchanged. Schema processing still prints three existing apple,tunable type conflicts from unchanged IOMMU/PCI/PHY bindings; these are outside this GPU binding and are recorded separately.
The final combined source is undergoing the M5 correctness/health gate. This PR is the final layer of the prepared stack; the complete tree will be folded into ending #1012 before its one Neo regression.