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soc: apple: sep: Bring up the M5 Pro (J714s) Secure Enclave - #1325

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DjDeveloperr merged 6 commits into
integration/aurorafrom
djdev/t6050-sep
Nov 9, 2026
Merged

DjDeveloperr merged 6 commits into
integration/aurorafrom
djdev/t6050-sep

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Adds the M5 Pro (J714s, T6050) to apple_sep: a platform profile and the device-tree pieces the driver needs to attach to the enclave iBoot leaves running.

  • dt-bindings: the T6050 SEP takes its mailbox through mboxes like every other SoC; the "must stay disabled" branch goes.
  • DT: the SEP's ASC v4 mailbox at sep + 0x8000 (ADT interrupts 533..536 in mailbox order) and the SEP DART window iBoot programmed (ADT dart-sep vm-base-0 0x10000004000, vm-size-0 0xffff0000, as on T8140).
  • DT: ps_sep is apple,firmware-owned. The enclave idles at actual 0 under auto-enable and gates itself for a sleep, so the pwrstate driver must not take it for off and write it.
  • DT: the SEP, its mailbox and DART move into die 0's soc@200000000. aura resolves the sep alias by path, and /soc names soc@200000000 first, so a node in the unit-less soc can't be reached.
  • DT: J714s gets the sep alias, through which aura reserves SEPFW and adds the iBoot and local-policy manifests. Without them the driver refuses to attach.
  • profile: T6040's, with the sensor bus at 0x505108000 (ADT /arm-io/spi2).

Everything stays disabled in-tree, following the T6050 inventory convention. A board or kit DT enables sep_mbox and ps_sep with its two fabric parents.

Tested on hardware (J714sAP, 2026-11-09)

RAM-booted kit kernel (these commits on the M5 kit base, with the s2r series under them), NVMe block devices read-only, xart_writes=0 provision_keybag=0:

  • binds: SEP platform profile: T6050/J714s
  • xART: APFS-resolved .gl extent (base 0x4df000); 170 slots, 14 live records, max revision 3067, 0 malformed ... writes disabled
  • attach: 7 endpoints, then the full ladder to 12 including the key store (0x12)
  • hwrng: registered after ready-phase survey (attempt 1)
  • sleep request (test-only trigger, not in this PR; the request word is the one the T8140 sleep series sends): answered in 61.8 ms, and the enclave gated its own domain: state 0x1000070f, the same value macOS leaves at its sleep commit.

Nothing was written to xART or the macOS volumes.

Offline: dt_binding_check for apple,sep.yaml passes; all eleven T6050 board DTs compile; SEP KUnit (on the kit base) 214 of 215 pass, 1 skipped (an unrelated G17 test that needs UCLAMP_TASK).

Not covered: Touch ID on J714s (sensor node, spi2 clock and power, calibration and root-key files, keybag provisioning).

🤖 Generated with Claude Code

…ilbox node

The T6050 SEP was described from the ADT with its four mailbox interrupts on
its own node and had to stay disabled. Its mailbox is an ASC v4 mailbox at the
SEP + 0x8000, as on the other SoCs, so describe it as its own node there and
require mboxes for every SEP. T6050 keeps its second reg and its clock.

Signed-off-by: Diljit Singh <hey@djdev.me>
iBoot hands over a running SEP on the M5 Pro (sepfw-booted in the J714sAP
ADT). Describe what apple_sep needs to attach to it: the ASC v4 mailbox at
the SEP + 0x8000, with the first four ADT interrupts in mailbox order (533
to 536: send empty, send not empty, receive empty, receive not empty), and
the DMA window iBoot programmed in the SEP DART (dart-sep vm-base-0
0x10000004000, vm-size-0 0xffff0000), which T8140 has too. Everything stays
disabled: a board enables the mailbox, and apple_sep enables the SEP and
its DART when it loads.

Signed-off-by: Diljit Singh <hey@djdev.me>
The J714sAP ADT (26A428) describes the enclave as J616s's: pre-booted
(sepfw-booted), an iop-sep,ascwrap-v6 SEP behind a DART whose window starts
at the BIT(40) alias (vm-base-0 0x10000004000, 0xffff0000 long), and J700's
Mesa sensor (sensor-id 0x3356) on spi2, here at 0x505108000, 8 MHz, chip
select 0. Take T6040's profile with that sensor bus.

Signed-off-by: Diljit Singh <hey@djdev.me>
iBoot starts the enclave, and the enclave gates its own domain for a
sleep (DEV_DISABLE in the state word, which macOS clears at the wake).
Its state word idles at actual 0 under auto-enable while it runs, so the
pwrstate driver would take it for off and write it. Mark it
firmware-owned: genpd keeps it on and never touches the register, and
the SEP driver reads the word itself.

Signed-off-by: Diljit Singh <hey@djdev.me>
The boot loader finds the SEP by the path a board's sep alias gives. The
inventory puts it in the unit-less soc node, and "/soc" names
soc@200000000 first, so such a path never reaches it, and the loader
could not reserve the SEP firmware or add its manifests. Move the SEP,
its mailbox and its DART into die 0's soc node, whose ranges cover them.

Signed-off-by: Diljit Singh <hey@djdev.me>
The boot loader finds the SEP through the sep alias: it reserves the
SEP firmware (ADT memory-map SEPFW) and adds the iBoot and local policy
manifests the enclave needs to open the machine's secure storage. Without
them apple_sep refuses to attach. J616s has the same alias.

Signed-off-by: Diljit Singh <hey@djdev.me>
@DjDeveloperr

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Retested before merging on the M5 Pro (J714sAP, bare metal, SSD boot), kernel 7.3.0-m5-merge: the M5's integration kernel with this round's rebased heads in place of the old ones (every PR's own patch identical to what is merged; logs in work/m5-pr-merge-20261109). CI green.

Before merging, this round (these 14 PRs, #1323 and the rebased #1254/#1306/#938/#1316/#1199) was test-merged in order onto integration/aurora f9cf6f9 with no conflicts: apple-dt-check.sh 414 → 414 warning lines (0 new) over 137 DTBs, all 20 changed bindings pass, and a local host-test run fails only where integration itself fails with this host's newer toolchain. A full arm64 build of the same set on 8d98b7a was clean.

  • apple_sep 502600000.sep: xart_writes=0 provision_keybag=0, SEP platform profile: T6050/J714s, xART resolved (170 slots, 14 live records, writes disabled), trusted-keys registered. Read-only, as intended on this rig.

🤖 Generated with Claude Code

@DjDeveloperr
DjDeveloperr merged commit 18d276c into integration/aurora Nov 9, 2026
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