drm/asahi, drm/apple: M5 GPU and firmware-27 display on integration/aurora

Documentation/devicetree/bindings/display/apple,dcp.yaml

@@ -97,13 +97,32 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 64
 
   clock-names:
     minItems: 1
-    items:
-      - const: clock-154
-      - const: clock-194
+    maxItems: 64
+
+  apple,clock-ids:
+    oneOf:
+      - type: boolean
+      - $ref: /schemas/types.yaml#/definitions/uint32-array
+        minItems: 1
+        maxItems: 64
+    description: |
+      Ordered firmware provider clock identifiers. Callback clock indices
+      select the corresponding entry in clocks. An explicitly empty table
+      is allowed when the provider has no clocks.
+
+  apple,firmware-physical-regs:
+    $ref: /schemas/types.yaml#/definitions/uint64-array
+    minItems: 1
+    maxItems: 10
+    description: |
+      Coprocessor physical base addresses in display register-table order,
+      including the bandwidth scratch and optional doorbell windows.
+      The number of entries must match the complete register table.
+      Omit on identity-mapped systems; reg supplies the physical view.
 
   memory-region:
     minItems: 1
@@ -446,12 +465,39 @@ allOf:
     then:
       required:
         - apple,bw-scratch
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum: ['apple,t6050-dcp', 'apple,t6050-dcpext']
+    then:
+      required:
+        - apple,clock-ids
+        - memory-region
+        - memory-region-names
+        - apple,firmware-compat
+      properties:
+        apple,firmware-compat:
+          items:
+            - const: 27
+            - const: 0
+            - const: 0
+    else:
+      properties:
+        clocks:
+          maxItems: 2
+        clock-names:
+          items:
+            - const: clock-154
+            - const: clock-194
+        apple,clock-ids: false
+        apple,firmware-physical-regs: false
   - if:
       not:
         properties:
           compatible:
             contains:
-              enum: ['apple,t8140-dcp', 'apple,t8140-dcpext']
+              enum: ['apple,t8140-dcp', 'apple,t8140-dcpext', 'apple,t6050-dcp', 'apple,t6050-dcpext']
     then:
       properties:
         apple,power-lut-data-x: false
@@ -463,7 +509,8 @@ allOf:
       properties:
         compatible:
           contains:
-            enum: ['apple,t8140-dcp', 'apple,t8140-dcpext']
+            enum: ['apple,t8140-dcp', 'apple,t8140-dcpext',
+                   'apple,t6050-dcp', 'apple,t6050-dcpext']
     then:
       properties:
         resets: false

Documentation/devicetree/bindings/gpu/apple,agx.yaml

@@ -17,6 +17,7 @@ properties:
           - apple,agx-g13s
           - apple,agx-g14g
           - apple,agx-g14s
+          - apple,agx-g17s
           - apple,agx-t6040
           - apple,agx-t6041
           - apple,agx-t6050
@@ -40,9 +41,11 @@ properties:
           - const: apple,agx-g14s
 
   reg:
+    minItems: 1
     maxItems: 2
 
   reg-names:
+    minItems: 1
     maxItems: 2
 
   power-domains:
@@ -200,6 +203,14 @@ properties:
       AFR leakage. Per-chip efuse values decoded by the boot loader,
       stored as IEEE-754 binary32 bit patterns in big-endian cells.
 
+  apple,leakage-calibration-words:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 3
+    maxItems: 3
+    description:
+      Raw per-chip GPU leakage calibration words for the M5 Pro controller
+      defaults. Supplied by the boot loader, never fixed in a board DT.
+
   apple,firmware-abi:
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 3
@@ -213,6 +224,46 @@ required:
   - reg
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: apple,agx-g17s
+    then:
+      description:
+        The M5 Pro GPU uses one MMIO range and two firmware mailbox roles.
+        Its firmware graph supplies the performance tables, so it has no
+        operating-point table in the board DT.
+      properties:
+        reg:
+          maxItems: 1
+        reg-names:
+          items:
+            - const: sgx
+        mboxes:
+          items:
+            - description: Primary GFX firmware mailbox
+            - description: Secondary GFX firmware mailbox
+        memory-region:
+          items:
+            - description: Region containing GPU MMU TTBs
+            - description: Region containing GPU MMU page tables
+            - description: Shared handoff structure for VM coordination
+            - description: Data segment of the loaded GPU firmware
+            - description: Firmware kernel-window page tables
+            - description: Text segment identifying the loaded GPU firmware
+        memory-region-names:
+          items:
+            - const: ttbs
+            - const: pagetables
+            - const: handoff
+            - const: fw-data
+            - const: l2-pagetables
+            - const: fw-text
+      required:
+        - power-domains
+        - reg-names
+        - memory-region-names
   - if:
       properties:
         compatible:
@@ -409,6 +460,7 @@ allOf:
                 - apple,agx-t6041
                 - apple,agx-t8132
                 - apple,agx-t8140
+                - apple,agx-g17s
     then:
       properties:
         reg:

Documentation/hwmon/macsmc-hwmon.rst

@@ -36,6 +36,13 @@ The driver leaves fan policy to the SMC until userspace writes a nonzero
 shutdown and removal release only fans taken over by such a request; resume
 does not reapply it. A new target write is required after resume.
 
+A kernel thermal policy (the M5 GPU governor) sets the fans through
+macsmc_hwmon_fans_request(), as a share of each fan's range, on every fan
+whose node names its mode, target, minimum and maximum keys, with or without
+apple,fan-manual-control. It uses the same manual mode, leaves fans userspace
+holds alone, and its fans return to the SMC at suspend, shutdown and removal
+like userspace's.
+
 SoC die temperatures are described by the ``apple,soc-die-keys`` string list
 on the hwmon device node. The driver appends these temperature channels after
 the ``temperature-*`` children, in list order, with labels ``SoC die <key>``.

arch/arm64/boot/dts/apple/t6050-j714s-gpu-panel.dtsi

@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * J714s internal panel, external display engines and GPU (G17S), for the boot
+ * loader's display and GPU handoff. Everything here stays disabled: the loader
+ * checks the ADT and the live DCP, DART and GPU firmware state, publishes the
+ * DCP's firmware properties and fills the GPU reservations, and only then
+ * enables the nodes, the GPU last. A loader without the handoff, or one whose
+ * checks fail, leaves the boot framebuffer to simpledrm and the GPU off.
+ *
+ * Values are from the J714sAP 27.0 ADT (dcp, dart-dcp, dart-disp0, dcpext*,
+ * dart-dcpext*, dart-dispext*, sgx, gfx-asc, gfx1-asc, pmgr) and the GPU
+ * firmware's own boot arguments (dArW, the two ASC wrappers).
+ */
+
+/ {
+	aliases {
+		/* The loader writes apple,notch-height into the "dcp" alias */
+		dcp = &dcp;
+		disp0 = &display;
+		/* The loader finds the GPU through this alias */
+		gpu = &sgx;
+	};
+
+	/* As on t6050-ultra.dtsi, with the internal display's DART (disp0, SID 0) */
+	display: display-subsystem {
+		compatible = "apple,display-subsystem";
+		iommus = <&disp0_dart 0>;
+		status = "disabled";
+	};
+
+	reserved-memory {
+		/* Filled and enabled by the loader from the ADT */
+		gpu_fw_text: gpu-fw-text {
+			reg = <0 0 0 0>;
+			no-map;
+			status = "disabled";
+		};
+
+		gpu_fw_data: gpu-fw-data {
+			reg = <0 0 0 0>;
+			no-map;
+			status = "disabled";
+		};
+
+		uat_ttbs: uat-ttbs {
+			reg = <0 0 0 0>;
+			no-map;
+			status = "disabled";
+		};
+
+		uat_pagetables: uat-pagetables {
+			reg = <0 0 0 0>;
+			no-map;
+			status = "disabled";
+		};
+
+		uat_l2_pagetables: uat-l2-pagetables {
+			reg = <0 0 0 0>;
+			no-map;
+			status = "disabled";
+		};
+
+		uat_handoff: uat-handoff {
+			reg = <0 0 0 0>;
+			no-map;
+			status = "disabled";
+		};
+	};
+};
+
+/* ADT dart-dcp and dart-disp0: vm-base 1 TiB, vm-size 3 TiB */
+&dcp_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&disp0_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&dcp {
+	/*
+	 * The 14.2-inch 3024x1964 mini-LED panel of J314/J414/J514. The OS takes
+	 * the dimensions from the ADT when it has them; this J714s ADT does not.
+	 */
+	panel {
+		compatible = "apple,panel-j714", "apple,panel-mini-led", "apple,panel";
+		width-mm = <302>;
+		height-mm = <196>;
+		adj-height-mm = <189>;
+	};
+};
+
+/*
+ * The four external display engines (dcpext0..3): the loader hands each over
+ * when its checks pass, else leaves it disabled. No display is described on
+ * them: dcpext0 loses its Type-C route, whose crossbar J714s keeps disabled.
+ */
+&dcpext0 {
+	/delete-property/ phys;
+	/delete-property/ phy-names;
+	/delete-property/ mux-controls;
+	/delete-property/ mux-control-names;
+	/delete-property/ apple,typec-dptx-phys;
+	/delete-property/ apple,typec-mux-indices;
+	/delete-property/ apple,connector-type;
+	/delete-node/ typec-routes;
+};
+
+/* The ADT lists no clocks for the external engines (clock-ids = []) */
+&dcpext1 {
+	apple,clock-ids;
+};
+
+&dcpext2 {
+	apple,clock-ids;
+};
+
+&dcpext3 {
+	apple,clock-ids;
+};
+
+/* ADT dart-dcpextN and dart-dispextN: vm-base 1 TiB, vm-size 3 TiB, as dcpext0's */
+&dcpext1_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&dispext1_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&dcpext2_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&dispext2_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&dcpext3_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+&dispext3_dart {
+	apple,dma-range = <0x100 0x0 0x300 0x0>;
+};
+
+/* The inventory ASC nodes; the mailboxes below describe the same windows. */
+/delete-node/ &gfx_asc;
+/delete-node/ &gfx1_asc;
+
+&{/soc} {
+	/*
+	 * ADT gfx-asc and gfx1-asc at their physical windows: the wrapper, the
+	 * 8-byte iop-vbar, and their second and third interrupts (send-empty,
+	 * recv-not-empty), as T8140/T8142.
+	 */
+	gfx_mbox: mailbox@2302600000 {
+		compatible = "apple,t6050-j775d-ascwrap-v6";
+		reg = <0x23 0x2600000 0x0 0x88000>,
+		      <0x23 0x2050000 0x0 0x8>;
+		reg-names = "wrapper", "iop-vbar";
+		interrupts = <AIC_IRQ 0 2797 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ 0 2800 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "send-empty", "recv-not-empty";
+		apple,firmware-role = "GFX";
+		power-domains = <&ps_gfx>;
+		#mbox-cells = <0>;
+		status = "disabled";
+	};
+
+	gfx1_mbox: mailbox@2302e00000 {
+		compatible = "apple,t6050-j775d-ascwrap-v6";
+		reg = <0x23 0x2e00000 0x0 0x88000>,
+		      <0x23 0x2850000 0x0 0x8>;
+		reg-names = "wrapper", "iop-vbar";
+		interrupts = <AIC_IRQ 0 2801 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ 0 2804 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "send-empty", "recv-not-empty";
+		apple,firmware-role = "GFX1";
+		power-domains = <&ps_gfx>;
+		#mbox-cells = <0>;
+		status = "disabled";
+	};
+};
+
+/* The ADT marks GPX and AFR, GFX's parents, critical. */
+&ps_gpx {
+	apple,always-on;
+};
+
+&ps_afr {
+	apple,always-on;
+};
+
+&sgx {
+	compatible = "apple,agx-g17s";
+	/* ADT sgx reg[0]; the driver maps the first 16 MiB as "sgx" */
+	reg = <0x23 0x0 0x0 0x3fdc000>;
+	reg-names = "sgx";
+	/delete-property/ interrupts;
+	mboxes = <&gfx_mbox>, <&gfx1_mbox>;
+	memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>,
+			<&gpu_fw_data>, <&uat_l2_pagetables>, <&gpu_fw_text>;
+	memory-region-names = "ttbs", "pagetables", "handoff", "fw-data",
+			      "l2-pagetables", "fw-text";
+};