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Achievement: Pull Sharkx2Achievement: Pair ExtraordinaireAchievement: YOLOAchievement: Starstruck

Achievements

Achievement: Pull Sharkx2Achievement: Pair ExtraordinaireAchievement: YOLOAchievement: Starstruck

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anlit75/README.md

Ting-An Cheng (Anson)

Digital IC Design Verification Engineer (DV) & Open Source Enthusiast specializing in RTL design, verification, and automation.

Tech Stack

🚀 IC Design & Verification

UVM SystemVerilog Verilog

🛠️ Others

Python C++ Docker Makefile LaTeX Git SVN GitHub Actions

Featured Work

Project What it solves Tech Stack Link
CCU-Thesis-LaTeX-Template Streamlines thesis and dissertation formatting for National Chung Cheng University students with a compliant LaTeX template. LaTeX Docker View Code
ChipForAll A Zero-Config Starter Kit for Open Source Silicon Design. Verilog Makefile Docker View Code
ADPLL Implements an All-Digital Phase-Locked Loop for precise clock synchronization in digital systems. Verilog View Code
RepoGallery Automates the creation of a personal portfolio website by aggregating GitHub repository data. Python GitHub Actions View Code

Connect

LinkedIn Email Website

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  1. CCU-Thesis-LaTeX-Template CCU-Thesis-LaTeX-Template Public template

    Unofficial LaTeX templates for both master's thesis and doctoral dissertations at National Chung Cheng University. 國立中正大學碩博士論文LaTex模板

    TeX 35 10

  2. ChipForAll ChipForAll Public template

    A Zero-Config Starter Kit for Open Source Silicon Design.

    Makefile

  3. ADPLL ADPLL Public

    All Digital Phase-Locked Loop (ADPLL)

    Verilog 26 8

  4. RepoGallery RepoGallery Public

    Just fork & good to go! A beautiful showcase for all your GitHub repos.

    Python 5 6

  5. SV-TBLab SV-TBLab Public

    SystemVerilog Testbench Workshop Lab

    SystemVerilog 3 2

  6. HDLBits HDLBits Public

    Verilog practice and solutions on HDLBits website

    Verilog