GB10 sm_121 latency kit versus NAK

Makefile

@@ -161,6 +161,15 @@ $(GPU_EW_TEST): tests/gpu_elementwise_test.c src/omega_gpu_elementwise_api.h $(O
 test-gpu-elementwise: $(GPU_EW_TEST)
 	./$(GPU_EW_TEST) --host-only
 
+# GB10 fixed-latency chains versus Mesa NAK. test-gpu-latmeas is host-only
+# (encode, disassemble, oracle, diff). The chip gate is tools/latmeas/run_spark.sh.
+.PHONY: test-gpu-latmeas
+GPU_LATMEAS_TEST = $(OUT_DIR)/gpu_latmeas_test
+$(GPU_LATMEAS_TEST): tests/gpu_latmeas_test.c $(OUT_DIR)/libomega_gpu.a
+	$(CC) $(CFLAGS) -ffp-contract=off -o $@ tests/gpu_latmeas_test.c $(OUT_DIR)/libomega_gpu.a -lpthread -lm
+test-gpu-latmeas: $(GPU_LATMEAS_TEST)
+	sh tools/latmeas/selftest.sh $(GPU_LATMEAS_TEST)
+
 # omega #308: structured warp reconvergence (BSSY/BSYNC regions). test-gpu-reconv is
 # host-only (encoder goldens, region bookkeeping, refusals, nvdisasm listing, every probe
 # kernel through the SIMT warp simulator tests/bw_warp_sim.h against the oracle, mutation
@@ -532,7 +541,7 @@ test-omega-slices:
 
 # Every host-only check: no GPU, no device opened. The chip gates are listed in README.md.
 # Portable commands and the AArch64-only rows are separated in docs/OMEGA_HOST_TESTS.md.
-HOST_TESTS = test-drift test-gpu-matmul-api test-gpu-elementwise test-gpu-reconv test-gpu-attention test-gpu-moe-window \
+HOST_TESTS = test-drift test-gpu-matmul-api test-gpu-elementwise test-gpu-latmeas test-gpu-reconv test-gpu-attention test-gpu-moe-window \
 	test-gpu-fp8 test-gpu-decode-attn test-gpu-router test-gpu-bf16-gemv test-gpu-fp8gemm test-gpu-tern-sched test-gpu-gpr-boundary \
 	test-gpu-cmdlist test-gpu-decode-graph test-gpu-code-alloc test-gpu-engine-compile test-gpu-engine \
 	test-gpu-engine-mutants test-gpu-engine-backend-compile test-gpu-engine-prod-build test-gpu-engine-sim \

evidence/LATMEAS-GB10-20261101-allanes/RECEIPT.md

@@ -0,0 +1,33 @@
+# GB10 all-lane latency run, 2026-11-01
+
+Second chip run of the latency kit. The operator reported the window as 2026-11-01 18:38–18:40Z. This directory is that output. The script did not write a `RECEIPT.txt` (that writer was added afterwards). The upload's sha256 is `ae4cdbcbfe7d15d2766f8d661cf35cbb88b7358fde20afcca5c441bd7071464f`. `sha256sum raw.json` is `565ece7ec537961bb70c66cdac7afea1cd6fdb0463e4ee70325a3bc528fce403`.
+
+`sm121_vs_NAK.md` is the table `fill_template.py` wrote from this `raw.json`. A fresh fill of the same file matches it.
+
+## What ran
+
+- Command: `sh tools/latmeas/run_spark.sh latmeas-out` (see `run.log`).
+- Launch rc 0. `raw.json` has `"error": ""`, `"launches": 1408`, `"runs": 11`, stall spread 0 on every case.
+- Tested tree: `c94c2c93442adf7fa24c22dee7e8a91bb1c93226` (`head.txt`). That commit is a merge of `4f3a4d0` (every lane stores four result words; HMMA reads `d0`..`d3`) and PR #251 `6a93cb567b33b67bc1185fb45a3c50fc4d88d30e`, with no other edits.
+- Doctor, from `run.log`: Linux 7.0.0-1019-nvidia aarch64, open module 580.173.02, GPU `000f:01:00.0` NVIDIA GB10 (sm_121), compiler 13.3.0, READY. The binary printed a 71 s upper bound. The script also printed a stale 90 s line; the binary is the bound.
+- Two home-directory paths in the log are replaced with `latmeas-out`.
+
+## Smallest passing stall
+
+Same as `evidence/LATMEAS-GB10-20261101/` (`03cdcc5`). From this `raw.json`:
+
+| case | stall_required |
+| --- | --- |
+| alu_alu | 4 |
+| fma_fma | 4 |
+| mixed | 5 |
+| pred | 13 |
+| fmnmx_alu | 4 |
+| imad_wide_lo | 3 |
+| hmma_reader | 20 |
+
+## What this file proves
+
+`run0_result` is lane 0's first result word at each stall. `reference_result` is null for every case. There is no host oracle, no per-lane count, and no `d1`..`d3` word in the JSON.
+
+The source at `4f3a4d0` sets a stall as passing only when all 32 lanes match all four result words (HMMA: the four `FADD` results; other cases: the result, the auxiliary word, and two zeros). A passing `stall_required` with spread 0 is what that check produced, and it landed on the same stalls as the lane-0 run. A reader of `raw.json` alone cannot see a lane bitmask or the four destination words. That recording is a later change and is not in this directory.

evidence/LATMEAS-GB10-20261101-allanes/diff.md

@@ -0,0 +1,21 @@
+# CUDA++ fixed latencies vs NAK
+
+Mesa commit `01bab9302a6bf0a082c7ba8c49d74427cf10b0cf`.
+Clock: nak_private.h:135 NAK_SV_CLOCK_LO = 0x50; from_nir.rs:3522 SM>=50 uses CS2R; sm70_encode.rs:4278 opcode 0x805, index bits 72..80.
+Priority 1 pairs match NAK on paper. They are measured because that match is circular.
+Rows below are the ones that differ. A blank NAK stall means NAK calls the op decoupled.
+
+| id | pair | CUDA++ | NAK | kernel |
+|---|---|---|---|---|
+| pred_attention | Predicate write -> guard, attention emitter | 13 | 13 + 1 = 14 | tests/gpu_latmeas_test.c (pred) |
+| hmma_reader | HMMA -> non-HMMA reader (FADD of d0) | 15 + NOP 14 = 29 | 19 + 9 = 28 | tests/gpu_latmeas_test.c (hmma_reader) |
+| imad_wide_lo | IMAD.WIDE low half -> IADD3 | 6 (blanket K_FIXED; IMAD.WIDE is not in fixed_pair_class) | 3 + 1 = 4 | tests/gpu_latmeas_test.c (imad_wide_lo) |
+| fmnmx_alu | FMNMX (dualalu) -> IADD3 (alu) | 6 (blanket K_FIXED; FMNMX is not in fixed_pair_class) | 4 + 1 = 5 | tests/gpu_latmeas_test.c (fmnmx_alu) |
+| qmma_reader | QMMA (IMMA) -> next reader | 15 + NOP 15 = 30 | 19 + 7 = 26 | not generated (patched QMMA placeholder; see REPRODUCE.md) |
+| numeric_min | Fixed-producer minimum in the numeric checker | 5 (any fixed producer; mixed pairs need 6) | 5 + 1 = 6 for mixed ALU/FMA | tests/gpu_latmeas_test.c (mixed) |
+| bssy | BSSY stall | 1, no scoreboard | decoupled (1 & sb) | not generated (NAK class is decoupled, not a fixed GPR RAW) |
+| bsync | BSYNC stall | 5, no scoreboard | decoupled (1 & sb) | not generated (NAK class is decoupled, not a fixed GPR RAW) |
+| bra | BRA stall | 5 | decoupled (1 & sb) | not generated (NAK class is decoupled, not a fixed GPR RAW) |
+| exit_op | EXIT stall | 5 | decoupled (1 & sb) | not generated (NAK class is decoupled, not a fixed GPR RAW) |
+| bar | BAR.SYNC stall | 6 | decoupled AGU (1 & sb) | not generated (NAK class is decoupled, not a fixed GPR RAW) |
+

evidence/LATMEAS-GB10-20261101-allanes/head.txt

@@ -0,0 +1 @@
+c94c2c93442adf7fa24c22dee7e8a91bb1c93226

evidence/LATMEAS-GB10-20261101-allanes/raw.json

@@ -0,0 +1,114 @@
+{
+  "kind": "cudapp-latmeas",
+  "synthetic": false,
+  "measured": true,
+  "mesa_commit": "01bab9302a6bf0a082c7ba8c49d74427cf10b0cf",
+  "driver": "NVRM version: NVIDIA UNIX Open Kernel Module for aarch64  580.173.02  Release Build  (dvs-builder@U22-A24-5-4)  Tue Jun 23 08:34:19 UTC 2026",
+  "machine": "aarch64",
+  "runs": 11,
+  "threads": 32,
+  "warps": 1,
+  "clock": "CS2R idx 0x50 (NAK_SV_CLOCK_LO)",
+  "launches": 1408,
+  "error": "",
+  "cases": {
+    "alu_alu": {
+      "stall_required": 4,
+      "stall_spread": 0,
+      "cycle_median": 2541,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 2477,
+      "cycle_spread_stall1": 0,
+      "overhead_cycle_median": 1261,
+      "reference_result": null,
+      "run0_result": [4026531840, 4026531840, 4026531840, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528],
+      "iters": 32,
+      "ops": 32,
+      "note": ""
+    },
+    "fma_fma": {
+      "stall_required": 4,
+      "stall_spread": 0,
+      "cycle_median": 2541,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 2477,
+      "cycle_spread_stall1": 0,
+      "overhead_cycle_median": 1261,
+      "reference_result": null,
+      "run0_result": [2139095040, 2139095040, 2139095040, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832, 1141112832],
+      "iters": 32,
+      "ops": 32,
+      "note": ""
+    },
+    "mixed": {
+      "stall_required": 5,
+      "stall_spread": 0,
+      "cycle_median": 4362,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 4170,
+      "cycle_spread_stall1": 9673,
+      "overhead_cycle_median": 1261,
+      "reference_result": null,
+      "run0_result": [4026531840, 4026531840, 4026531840, 1024, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072],
+      "iters": 32,
+      "ops": 64,
+      "note": ""
+    },
+    "pred": {
+      "stall_required": 13,
+      "stall_spread": 0,
+      "cycle_median": 2714,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 70,
+      "cycle_spread_stall1": 0,
+      "overhead_cycle_median": 1261,
+      "reference_result": null,
+      "run0_result": [3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 3735928559, 32, 32, 32],
+      "iters": 32,
+      "ops": 32,
+      "note": ""
+    },
+    "fmnmx_alu": {
+      "stall_required": 4,
+      "stall_spread": 0,
+      "cycle_median": 2541,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 2507,
+      "cycle_spread_stall1": 0,
+      "overhead_cycle_median": 1261,
+      "reference_result": null,
+      "run0_result": [4026531840, 4026531840, 4026531840, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072, 704643072],
+      "iters": 32,
+      "ops": 32,
+      "note": ""
+    },
+    "imad_wide_lo": {
+      "stall_required": 3,
+      "stall_spread": 0,
+      "cycle_median": 2768,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 2736,
+      "cycle_spread_stall1": 0,
+      "overhead_cycle_median": 1261,
+      "reference_result": null,
+      "run0_result": [32, 32, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528, 528],
+      "iters": 32,
+      "ops": 32,
+      "note": ""
+    },
+    "hmma_reader": {
+      "stall_required": 20,
+      "stall_spread": 0,
+      "cycle_median": 63,
+      "cycle_spread": 0,
+      "cycle_median_stall1": 61,
+      "cycle_spread_stall1": 0,
+      "overhead_cycle_median": 49,
+      "reference_result": null,
+      "run0_result": [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648, 1098907648],
+      "iters": 1,
+      "ops": 1,
+      "note": ""
+    }
+  }
+}