[abmajith]

• third_party/cve2, third_party/ibex: submodules at pinned commits, wrapped by rtl/cores/{cve2,ibex}/rabbit_cpu.sv (deviations from the contract documented: boot/mtvec placement, fast interrupt priority lowest-first, Ibex has 15 fast lines). CORE_CFLAGS in core.mk lets firmware know about documented deviations; the irq test uses it for the priority order.
• Ibex files.f generated from its FuseSoC cores (tools/fusesoc_to_filelist.py); synth_sky130.sh works around one construct slang cannot elaborate.
• Fixed in our testbench: reset started low, so Verilator never saw a falling edge and cores that gate their clock during reset (CVE2) kept unreset state (CVE2 ran in user mode; CV32E40P's mcountinhibit was not reset, so earlier CV32E40P mcycle-based timings were wrong).
• Timing measurements in firmware use the SoC cycle counter (mcycle is stopped at reset on CV32E40P).
• rtl/cores/README.md: area / delay / cycles / M timing / interrupt-during- divide for rabbit3, rabbit5, Ibex, CVE2, CV32E40P, all from our scripts.
• CI: lint and soc-sim matrices include cve2 and ibex.