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rabbit5 v0: own timing-predictable RV32I 5-stage core, formally verified - #13
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abmajith
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Nov 6, 2026
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- rtl/cores/rabbit5: readable SystemVerilog pipeline (IF/ID/EX/MEM/WB), full forwarding, 1-cycle load-use stall, all redirects resolved in EX (fixed 2-cycle penalty), M-mode CSRs and traps, RVFI port; plugs into the rabbit_cpu contract and runs the same hello firmware as CV32E40P
- dv/formal/rabbit5: riscv-formal (submodule) flow via a slang-converted core and a build-time mirror; 45/45 checks pass
- dv/formal/rabbit5/timing: own timing properties T1 (exact retirement gap model), T2 (first retirement), T3 (memory slot), with covers for every case and the 6..16 throughput bounds
- make gls-smoke: Yosys generic netlist runs hello in the same 3958 cycles
- CI: rabbit5 in lint/soc-sim matrices, formal job, GLS netlist + smoke
- fix: firmware build dir is now per core (CV32E40P was running an RV32I image built for rabbit5)
- docs: rabbit5 review guide; remove links to research notes kept outside the repo
- rtl/cores/rabbit5: readable SystemVerilog pipeline (IF/ID/EX/MEM/WB), full forwarding, 1-cycle load-use stall, all redirects resolved in EX (fixed 2-cycle penalty), M-mode CSRs and traps, RVFI port; plugs into the rabbit_cpu contract and runs the same hello firmware as CV32E40P - dv/formal/rabbit5: riscv-formal (submodule) flow via a slang-converted core and a build-time mirror; 45/45 checks pass - dv/formal/rabbit5/timing: own timing properties T1 (exact retirement gap model), T2 (first retirement), T3 (memory slot), with covers for every case and the 6..16 throughput bounds - make gls-smoke: Yosys generic netlist runs hello in the same 3958 cycles - CI: rabbit5 in lint/soc-sim matrices, formal job, GLS netlist + smoke - fix: firmware build dir is now per core (CV32E40P was running an RV32I image built for rabbit5) - docs: rabbit5 review guide; remove links to research notes kept outside the repo Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
abmajith
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Nov 6, 2026
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Will Check further with refinement on the rabbit3 core
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