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[minor-cpu] Support CoreMark workloads.#440

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AnZhong24 merged 2 commits into
Synthesys-Lab:masterfrom
AnZhong24:master
Jun 9, 2026
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[minor-cpu] Support CoreMark workloads.#440
AnZhong24 merged 2 commits into
Synthesys-Lab:masterfrom
AnZhong24:master

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[examples/minor-cpu/src] Add subword load/store decoding, masked stores, sign/zero extension, branch epoch filtering, and stricter workload asset handling.

[examples/minor-cpu/utils/loader.py] Load allocatable ELF sections directly so text, rodata, data, and bss-style regions are represented in workload images.

[examples/minor-cpu/workloads] Add CoreMark packaging/check support and a packaged coremark workload image without committing ELF/dump build byproducts.

[examples/minor-cpu/unit-tests] Add data images required by the newly enabled lbu and sb unit tests.

An Zhong added 2 commits June 8, 2026 14:33
[examples/minor-cpu/src] Add subword load/store decoding, masked stores, sign/zero extension, branch epoch filtering, and stricter workload asset handling.

[examples/minor-cpu/utils/loader.py] Load allocatable ELF sections directly so text, rodata, data, and bss-style regions are represented in workload images.

[examples/minor-cpu/workloads] Add CoreMark packaging/check support and a packaged coremark workload image without committing ELF/dump build byproducts.

[examples/minor-cpu/unit-tests] Add data images required by the newly enabled lbu and sb unit tests.
[python] Filter lower ESI passes through either FINAL_LOWERING_PASSES or PASS_PHASES so generated Verilog designs work across PyCDE pass-list APIs.

[tests] Update the generated header test to cover the compatibility block.
@AnZhong24 AnZhong24 merged commit 4662b2f into Synthesys-Lab:master Jun 9, 2026
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