Float opcodes have inconsistent encoding formats

[SuperInstance]

Problem

Float arithmetic and comparison opcodes use different encoding formats within the same category:

• FADD, FSUB, FMUL, FDIV: Format E (4 bytes: [opcode][fd][fs1][fs2]) — 3 register operands
• FNEG, FABS: Format C (3 bytes: [opcode][fd][fs1]) — 2 register operands, reads fd as input
• FMIN, FMAX: Format C (3 bytes: [opcode][fd][fs1]) — 2 register operands, computes min/max of both
• FEQ, FLT, FLE, FGT, FGE: Format C (3 bytes) — 2 register operands

Impact

• Implementors must memorize which float ops are 2-operand vs 3-operand
• FMIN/FMAX read fd as an input (min(F[fs1], F[fd])), which is non-obvious
• No consistent pattern to predict encoding from functionality

Proposed Fix

1. Document the encoding format per opcode in ISA spec
2. Consider normalizing all binary float ops to Format E for consistency
3. At minimum, add a comment block in opcodes.py grouping by format

Discovered By

Super Z — flux-conformance suite (session 9, 2026-04-12)