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@Rodolfo-Pellizzoni-Lab

Rodolfo Pellizzoni - Lab

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  1. he-soc he-soc Public

    This is the multicore AlSaqr-variant of the PULP he-soc platform. It has a coherent interconnect based on the AXI4 ACE protocol, called Culsans.

    SystemVerilog 1 1

  2. ibex-apmu ibex-apmu Public

    Forked from Arshaan-256/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. This core has been extended to meet the APMU design specification, and is being used as the APMU processor.

    SystemVerilog

  3. apmu-software apmu-software Public

    C

  4. alsaqr-mcp alsaqr-mcp Public

    Python

Repositories

Showing 4 of 4 repositories
  • he-soc Public

    This is the multicore AlSaqr-variant of the PULP he-soc platform. It has a coherent interconnect based on the AXI4 ACE protocol, called Culsans.

    Rodolfo-Pellizzoni-Lab/he-soc's past year of commit activity
    SystemVerilog 1 1 0 0 Updated Oct 16, 2026
  • alsaqr-mcp Public
    Rodolfo-Pellizzoni-Lab/alsaqr-mcp's past year of commit activity
    Python 0 0 0 0 Updated Oct 16, 2026
  • apmu-software Public
    Rodolfo-Pellizzoni-Lab/apmu-software's past year of commit activity
    C 0 MIT 0 0 0 Updated Sep 18, 2026
  • ibex-apmu Public Forked from Arshaan-256/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. This core has been extended to meet the APMU design specification, and is being used as the APMU processor.

    Rodolfo-Pellizzoni-Lab/ibex-apmu's past year of commit activity
    SystemVerilog 0 Apache-2.0 828 0 0 Updated Sep 17, 2024

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