A Windows CPU and DDR5 memory tuning tool for supported Intel LGA1700 and AMD Ryzen systems. Adjust clocks, power limits, voltages and Curve Optimizer in a compact light/dark interface. Available controls depend on your hardware and BIOS.
- Download the package from Releases.
- Extract the entire folder—keep the bundled driver and support files beside
Roch CPU.exe. - Run
Roch CPU.exeas administrator. Current-source framework-dependent builds need the .NET 10 Desktop Runtime (x64); self-contained builds do not. Older releases targeting .NET 8 still need the .NET 8 runtime.
Windows 10/11 x64 is required. If Windows blocks a driver, some controls will be unavailable.
- Intel tuning: supported core, E-core and ring ratios, voltage offsets/overrides, and PL1/PL2 power limits. BIOS locks and CPU/chipset restrictions still apply.
- AMD Ryzen tuning: PPT, TDC, EDC, thermal limit, PBO scalar and supported FMax controls through the SMU.
- Per-core Curve Optimizer: edit individual AMD core offsets, refresh hardware readings and apply changes from a dedicated window.
- DDR5 memory voltages: per-DIMM VDD, VDDQ and VPP controls where the PMIC permits writes, with calibration and read-back checks.
- Board-specific controls: CPU Core override, base clock and CPU VDD2 on supported MSI Intel 600/700-series boards. Core override updates both the Renesas regulator and Intel OC mailbox, with read-back and rail verification. AMD BCLK writing is not enabled on the tested B850MPOWER.
- Light and dark modes: grouped clock, power, boost and memory sections, editable values and a log explaining rejected or unavailable settings.
- Social links: YouTube | X | Discord in the bottom-left footer, matching Roch Viewer.
- Hardware-read header: CPU, core/thread topology, microcode, motherboard and BIOS values are labeled consistently above the controls.
- Intel voltage read-back: programmed Core, E-core L2, Ring, SA and GT targets are shown when firmware supplies them. On supported MSI boards, Core displays the regulator target rather than a potentially stale mailbox-only value; an adaptive Ring with no encoded target displays the real shared IA/core-rail voltage instead of
Auto. - Apply and Reset: Apply writes your edits; Reset restores the tool's startup baseline where supported.
Controls vary by processor, motherboard, BIOS and driver access. Optional PawnIO enables AMD SMU power-table read-back for PPT/TDC/EDC; Roch CPU does not install it automatically. See the hardware reference for platform details.
Left: Roch CPU 1.0.3 on an Intel Core i5-14600KF / Z790MPOWER, including the board-backed Core override and numeric adaptive Ring voltage. Right: the latest real AMD-hardware capture, Roch CPU 1.0.2 on an AMD Ryzen 7 9850X3D. Available rows follow the detected hardware. Displayed settings are examples, not tuning recommendations.
Install the .NET 10 SDK, then run:
build.cmd --self-containedOpen dist\Roch CPU.exe. The current version is 1.0.3.
Overclocking can cause crashes, data loss or hardware damage. Change one setting at a time and test stability. Read-back checks do not prove a setting is stable.
- Ivan Rusanov — ZenStates-Core, ZenStates and SMUDebugTool: references for AMD SMU messages, mailbox addresses and Curve Optimizer core mapping.
- OpenLibSys / Noriyuki Miyazaki: the bundled WinRing0 low-level access driver.
- LibreHardwareMonitor: Super I/O register/access references and the source package for the bundled WinRing0 binary.
- namazso — PawnIO and PawnIO.Modules: optional driver access and the bundled signed RyzenSMU module for AMD power-table reads.
- ryzen_smu: AMD SMN access reference.
Created by Roch Studio / @MateoPCTech. See third-party notices for attribution, component licenses and implementation details.


