[CI] Fix CT W4A16 e2e memory-wait timeout on Strix Halo CI runner#991
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On Strix Halo runners amdsmi reports only 512 MiB dedicated VRAM, of which ~314 MiB (61%) is already occupied by the ROCm baseline before any test runs. The memory-wait threshold is (1 - gpu_memory_utilization), so with gpu_memory_utilization=0.5 the threshold was 50% = 256 MiB — below the 314 MiB floor, making it impossible to satisfy in 120 s. Lower gpu_memory_utilization to 0.35, giving threshold = 65% = 332 MiB, which is safely above the 314 MiB baseline. vLLM uses unified memory on Strix Halo (PyTorch sees ~28+ GiB), so the KV-cache budget remains positive at this utilization ratio. Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
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AndreasKaratzas
amd-callumm
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Jun 9, 2026
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On Strix Halo runners amdsmi reports only 512 MiB dedicated VRAM, of which ~314 MiB (61%) is already occupied by the ROCm baseline before any test runs. The memory-wait threshold is (1 - gpu_memory_utilization), so with gpu_memory_utilization=0.5 the threshold was 50% = 256 MiB — below the 314 MiB floor, making it impossible to satisfy in 120 s.
Lower gpu_memory_utilization to 0.35, giving threshold = 65% = 332 MiB, which is safely above the 314 MiB baseline. vLLM uses unified memory on Strix Halo (PyTorch sees ~28+ GiB), so the KV-cache budget remains positive at this utilization ratio.
Fixes CI failure like https://github.com/ROCm/vllm/actions/runs/27040820558 when running the the runner with 512 MiB VRAM.