Squashed upstream AMDGPU CFI series

[slinder1]

Series ends at llvm#183147

Below are the original commit messages:

This is the commit message #1:

[MIR] Error on signed integer in getUnsigned

Previously we effectively took the absolute value of the APSInt, instead diagnose the unexpected negative value.

This is the commit message #2:

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi instructions makes .s/.mir files more readable, and it is necessary to support updating registers in CFI instructions (something that the AMDGPU backend requires).

This is the commit message #3:

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see https://bugs.llvm.org/show_bug.cgi?id=37240) we want to enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier should be explored.

This is the commit message #4:

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the outer-most frame. This implies they can only have a meaningful definition for the CFA, which AMDGPU defines using a memory location description with a literal private address space address. The return address is set to undefined as a sentinel value to signal the end of unwinding.

Co-authored-by: Scott Linder scott.linder@amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu@amd.com

This is the commit message #5:

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles during PEI. The remaining spills are handled in a subsequent patch.

Co-authored-by: Scott Linder scott.linder@amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu@amd.com

This is the commit message #6:

[AMDGPU] Use register pair for PC spill

This is the commit message #7:

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on conventions for how spills are placed within the entry block. The approach in this change produces larger unwind tables, with the increased size being spent on additional DW_CFA_advance_location instructions needed to describe the unwinding accurately.

Co-authored-by: Scott Linder scott.linder@amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu@amd.com

This is the commit message #8:

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly where CFI is emitted avoids the need to invent a mechanism to track them from ISel.

Co-authored-by: Scott Linder scott.linder@amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu@amd.com

This is the commit message #9:

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I347842ab4dd75f19d6d4c0537112de610571c12e

[z1-cciauto]

PSDB Build Link: http://mlse-bdc-20dd129:8065/#/builders/6/builds/196

[dstutt]

Is the intent with this to make the merge from upstream easier?
Presumably all the commits have been through review upstream already? (If so, then I'd be happy to approve this one on that basis).

[slinder1]

Is the intent with this to make the merge from upstream easier?

That was the goal, and if another approach would be preferred I'm open to it. This can also just be a reference for doing the merge.

Presumably all the commits have been through review upstream already? (If so, then I'd be happy to approve this one on that

Yes