[LLVM][FlyDSL] Bump up LLVM and Adapt FlyDSL to upstream LLVM/MLIR API changes by jli-melchior · Pull Request #945 · ROCm/FlyDSL

jli-melchior · 2026-07-31T04:15:44Z

Motivation

Adapt FlyDSL to LLVM API changes. This PR updates both C++ and Python layers to match upstream LLVM/ROCDL breaking changes.

Technical Details

C++ changes

OpaqueProperties → PropertyRef
getType() → getSourceElementType() for GEP
getSizeInBits() → getTypeSizeInBits()
MFMA/WMMA enum attribute constructors

Python compat wrappers (expr/rocdl/init.py)

MFMA blgp: int → #rocdl<mfma_perm_b ...> attribute
MFMA scale cbsz/blgp: int → #rocdl<matrix_format ...> attribute
WMMA fmtA/fmtB/modC/scaleType/fmtScale: int → ROCDL enum attributes
sched_barrier/sched_group_barrier: int mask → #rocdl<sched_group_mask ...> attribute
buffer_load/buffer_store/buffer_load_lds: aux from positional Value → keyword Attribute
buffer_atomic_fadd/buffer_atomic_fmax: added leading res type, aux as keyword Attribute
tensor_load_to_lds/tensor_store_from_lds: cache_policy as keyword Attribute
global_prefetch: scope from positional → cache_policy keyword

Compiler/backend

gpu.func kernel attribute: accept both "kernel" and "gpu.kernel"
waves_per_eu: use native rocdl.waves_per_eu attribute instead of passthrough string

Build infrastructure

llvm-hash.txt → llvm-build-info.json

Known regressions from LLVM base update (to investigate separately)

test_conv3d_implicit_fp8[1-96-4-8-9-96-1-1]: rel_err 0.31 (threshold 0.05)
test_rmsnorm_dynamicquant: quant diff 116 on M=64, N=2000, f32

Test Plan

Test Result

Submission Checklist

Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

coderfeli · 2026-08-05T07:16:16Z

@jli-melchior still failed.

Update build scripts to read repo/commit from internal-llvm-build-info.json and tag build/install directories with the commit short hash. Fix C++ API breakage introduced by the internal LLVM: - OpaqueProperties → PropertyRef in inferReturnTypes - Buffer op aux parameter from Value → Attribute - Atomic buffer ops now require explicit result Type - MFMA blgp parameter from IntegerAttr → MFMAPermB enum - MFMA scale cbsz/blgp from IntegerAttr → MatrixFormat enum - WMMA modC from raw uint16_t → WMMACModifier enum - WMMA scale params from raw casts → typed ROCDL enums - TDM cachePolicy from uint32_t → Attribute - DenseMapInfo: remove sentinel keys (tombstone-free hashing) Co-Authored-By: Claude <noreply@anthropic.com>

Consolidate internal-llvm-build-info.json and llvm-hash.txt into a single thirdparty/llvm-build-info.json with "upstream" and "internal" entries. Build scripts select by key name: - build_llvm.sh reads ['upstream'] - build_internal_llvm.sh / build_internal_flydsl.sh read ['internal'] Update CI workflows (build-whl, flydsl, build-custom-llvm-tools) to use llvm-build-info.json for cache keys and commit lookups. Co-Authored-By: Claude <noreply@anthropic.com>

Co-Authored-By: Claude <noreply@anthropic.com>

The internal LLVM update changed several ROCDL ops: operands became keyword-only attributes (aux, mask, cache_policy) and WMMA sign params were removed. Add compatibility wrappers in expr/rocdl so downstream callers (e.g. aiter) continue to work without source changes. - raw_ptr_buffer_load: accept aux as positional, convert Value/int → Attr - raw_ptr_buffer_load_lds: same aux handling - sched_barrier / sched_group_barrier: convert int mask → SchedGroupMask enum attr - tensor_load_to_lds / tensor_store_from_lds: accept cache_policy as positional - tdm_ops: pass cache_policy as keyword to underlying ROCDL ops Co-Authored-By: Claude <noreply@anthropic.com>

The internal LLVM update changed WMMA op parameters (fmtA, fmtB, modC, scaleAType, scaleBType, fmtScaleA, fmtScaleB) from plain integers to typed ROCDL enum attributes. Add int-to-enum conversion in the existing wmma_scale_f32_16x16x128_f8f6f4, wmma_scale_f32_32x16x128_f4, and wmma_f32_16x16x128_fp8_fp8 wrappers so downstream callers passing ints continue to work. Co-Authored-By: Claude <noreply@anthropic.com>

RawPtrBufferLoadOp/StoreOp aux changed from a positional Value operand to a keyword-only Attribute in the internal LLVM update. Convert the cache_modifier int to IntegerAttr and pass as keyword. Co-Authored-By: Claude <noreply@anthropic.com>

global_prefetch's second param changed from positional `scope` to keyword-only `cache_policy` in the LLVM binding regeneration. l2_prefetch_tile was the only call site missed — fix it to use cache_policy=_cache_policy_attr(scope), consistent with the tensor_load_to_lds/tensor_store_from_lds fixes in the same file. Co-Authored-By: Claude <noreply@anthropic.com>

Co-Authored-By: Claude <noreply@anthropic.com>

The upstream LLVM changed blgp from I32Attr to ROCDL_MFMAPermBAttr and cbsz/blgp in mfma_scale from I32Attr to ROCDL_MatrixFormatAttr. The AttrBuilder is not registered for these enum types, so passing a plain int causes std::bad_cast at op creation time. Add _blgp_attr() to convert int blgp values to #rocdl<mfma_perm_b ...> attributes in _split_mfma_operands, and reuse _wmma_fmt() for the mfma_scale cbsz/blgp (ROCDL_MatrixFormatAttr). Co-Authored-By: Claude <noreply@anthropic.com>

…tribute The upstream LLVM added a leading `res` (result type) parameter to raw_ptr_buffer_atomic_fadd/fmax and changed `aux` from positional Value to keyword-only Attribute. The old wrapper passed vdata as the first arg, which was misinterpreted as the result type causing std::bad_cast. Infer the result type from vdata.type, convert int aux to IntegerAttr, and pass aux as keyword. Co-Authored-By: Claude <noreply@anthropic.com>

Upstream LLVM renamed the gpu.func kernel marker attribute from "gpu.kernel" to "kernel". The _iter_gpu_kernel_funcs helper failed to match any kernel functions, so lower_compile_hints silently skipped the waves_per_eu passthrough override. Accept both "kernel" and "gpu.kernel" for backward compatibility. Co-Authored-By: Claude <noreply@anthropic.com>

Upstream LLVM now lowers rocdl.waves_per_eu directly to the LLVM IR "amdgpu-waves-per-eu" function attribute. The old approach of deleting the native attribute and adding a passthrough string no longer works. Set rocdl.waves_per_eu directly with the override value. Update tests to match the new single-value format ("2" instead of "2,2"). Co-Authored-By: Claude <noreply@anthropic.com>

Upstream LLVM/MLIR changed rocdl.mfma.scale to print cbsz and blgp as enum keywords (fp8_e4m3, fp8_e5m2, fp4_e2m1) instead of raw integers. Update the three CHECK lines in mma_atom_stateful.mlir to match.

- mma_scale_gfx1250.mlir: wmma.scale/scale16 ops now print named enum keyword attrs (fmtA, fmtB, modC, scaleAType, ...) instead of integer dict attrs; modC=1 prints as "neg" instead of "1 : i16". - tdm_gfx1250.mlir: tensor.load.to.lds / tensor.store.from.lds changed cachepolicy from keyword syntax ("cachepolicy 0") to positional (", 0").

The upstream LLVM narrowed scaleAType/scaleBType to a 2-value enum (WMMAMatrixScale: row0=0, row1=1). The old verifier accepted [0,3] but the static_cast to the enum produces malformed IR for values 2 and 3. Tighten the verifier range to [0,1] and fix the fp4_opsel FileCheck test to use opselB=1 (row1) instead of opselB=2 (out-of-range). No shipping kernels are affected — all gfx1250 WMMAScale kernels default opsel to 0. Co-Authored-By: Claude <noreply@anthropic.com>

sjfeng1999 · 2026-08-07T08:16:46Z

+def _mask_to_attr(mask):
+    """Convert an int or keyword mask to a SchedGroupMask attribute."""
+    from ..._mlir import ir as _ir
+
+    if isinstance(mask, _ir.Attribute):
+        return mask
+    if isinstance(mask, str):
+        return _ir.Attribute.parse(f"#rocdl<sched_group_mask {mask}>")
+    val = int(mask)
+    if val == 0:
+        return _ir.Attribute.parse("#rocdl<sched_group_mask none>")
+    parts = [kw for bit, kw in _SCHED_MASK_INT_TO_KW.items() if bit and val & bit]
+    if not parts:
+        return _ir.Attribute.parse("#rocdl<sched_group_mask none>")
+    return _ir.Attribute.parse(f"#rocdl<sched_group_mask {'|'.join(parts)}>")
+
+
+@dsl_loc_tracing
+def sched_barrier(mask, **kw):
+    return _ods_sched_barrier(_mask_to_attr(mask), **kw)
+
+
+@dsl_loc_tracing
+def sched_group_barrier(mask, size, group_id, **kw):
+    return _ods_sched_group_barrier(_mask_to_attr(mask), size, group_id, **kw)
+

 @dsl_loc_tracing
 def sched_mfma(cnt):
    sched_group_barrier(mask_mfma, cnt, 0)


 @dsl_loc_tracing
 def sched_vmem(cnt):
    sched_group_barrier(mask_vmem_rd, cnt, 0)


 @dsl_loc_tracing
 def sched_dsrd(cnt):
    sched_group_barrier(mask_dsrd, cnt, 0)


Map a instruction type to a op_code then remap it back to the original instruction type?

Map a instruction type to a op_code then remap it back to the original instruction type?

This wrapper converts the int mask that existing kernels pass (e.g. sched_barrier(0x008)) to the new ROCDL enum attribute type. It preserves backward compatibility so callers don't need to change.

sjfeng1999 · 2026-08-07T08:27:44Z

+_WMMA_FMT_INT_TO_KW = {
+    0: "fp8_e4m3",
+    1: "fp8_e5m2",
+    2: "fp6_e2m3",
+    3: "fp6_e3m2",
+    4: "fp4_e2m1",
+}
+_WMMA_MODC_INT_TO_KW = {0: "none", 1: "neg", 2: "abs", 3: "neg_abs"}
+_WMMA_SCALE_TYPE_INT_TO_KW = {0: "row0", 1: "row1"}
+_WMMA_SCALE_FMT_INT_TO_KW = {0: "e8", 1: "e5m3", 2: "e4m3"}
+
+
+def _wmma_attr(val, mapping, attr_name):
+    """Convert an int to a parsed ROCDL enum attribute for WMMA ops."""
+    from ..._mlir import ir as _ir
+
+    if val is None or isinstance(val, _ir.Attribute):
+        return val
+    if isinstance(val, bool):
+        return val
+    kw = mapping.get(int(val))
+    if kw is None:
+        return val
+    return _ir.Attribute.parse(f"#rocdl<{attr_name} {kw}>")
+
+
+def _wmma_fmt(val):
+    return _wmma_attr(val, _WMMA_FMT_INT_TO_KW, "matrix_format")
+
+
+def _wmma_modc(val):
+    return _wmma_attr(val, _WMMA_MODC_INT_TO_KW, "wmma_c_modifier")
+
+
+def _wmma_scale_type(val):
+    return _wmma_attr(val, _WMMA_SCALE_TYPE_INT_TO_KW, "wmma_matrix_scale")
+
+
+def _wmma_scale_fmt(val):
+    return _wmma_attr(val, _WMMA_SCALE_FMT_INT_TO_KW, "wmma_matrix_scale_format")
+
+


We could update to use the new rocdl.enums instead. No need to keep backward compatibility because these raw mlir ops are not the part of stable apis.

Indeed this is for backward compatibility, removing the wrappers would require updating many operators in the aiter repo. The raw mlir ops in the upstream are indeed not stable. Is it better to keep this wrapper for the maintenance of aiter operators?

Update test_wmma_scale_type_roundtrip to use opsel_b=1 instead of opsel_b=2, matching the tightened verifier range [0,1]. Co-Authored-By: Claude <noreply@anthropic.com>

jli-melchior changed the title ~~[llvm] bump up llvm for upstream and internal coexec opt and adapt flydsl api~~ [wip][llvm][flydsl] bump up llvm for upstream and internal coexec opt and adapt flydsl api Jul 31, 2026

jli-melchior changed the title ~~[wip][llvm][flydsl] bump up llvm for upstream and internal coexec opt and adapt flydsl api~~ [WIP][LLVM][Flydsl] bump up llvm for upstream and internal coexec opt and adapt flydsl api Jul 31, 2026

Boss2002n force-pushed the jli/update-llvm-basemain branch 3 times, most recently from 0694bb6 to fc5250c Compare August 5, 2026 05:46

Boss2002n force-pushed the jli/update-llvm-basemain branch from 58cc8b2 to 9bb26a4 Compare August 5, 2026 07:28

jli-melchior changed the title ~~[WIP][LLVM][Flydsl] bump up llvm for upstream and internal coexec opt and adapt flydsl api~~ [WIP][LLVM][FlyDSL] Bump up LLVM and Adapt FlyDSL to upstream LLVM/MLIR API changes Aug 5, 2026

Boss2002n force-pushed the jli/update-llvm-basemain branch from 9d6415a to 966c4b0 Compare August 6, 2026 02:44

jli-melchior changed the title ~~[WIP][LLVM][FlyDSL] Bump up LLVM and Adapt FlyDSL to upstream LLVM/MLIR API changes~~ [LLVM][FlyDSL] Bump up LLVM and Adapt FlyDSL to upstream LLVM/MLIR API changes Aug 7, 2026

Boss2002n force-pushed the jli/update-llvm-basemain branch from 2fe5e75 to 67b0bda Compare August 7, 2026 02:19

coderfeli requested a review from sjfeng1999 August 7, 2026 06:41

jli-melchior and others added 18 commits August 7, 2026 07:38

[llvm] add build script for internal llvm

9cbad1d

[style] clang-format C++ files touched by LLVM API adaptation

fd2e9a5

Co-Authored-By: Claude <noreply@anthropic.com>

[style] black + ruff format compat changes

97a1be8

Co-Authored-By: Claude <noreply@anthropic.com>

[style] reformat compat changes with CI-matching black

49f318b

Co-Authored-By: Claude <noreply@anthropic.com>

[compat] Update mma_atom_stateful FileCheck for ROCDL enum cbsz/blgp

185433b

Upstream LLVM/MLIR changed rocdl.mfma.scale to print cbsz and blgp as enum keywords (fp8_e4m3, fp8_e5m2, fp4_e2m1) instead of raw integers. Update the three CHECK lines in mma_atom_stateful.mlir to match.

[build] update scritpt

c63c241

Boss2002n force-pushed the jli/update-llvm-basemain branch from 9e029b6 to 69523e6 Compare August 7, 2026 07:38

sjfeng1999 reviewed Aug 7, 2026

View reviewed changes

[compat] Fix gfx1250 wmma_scale roundtrip test for narrowed opsel range

48c732b

Update test_wmma_scale_type_roundtrip to use opsel_b=1 instead of opsel_b=2, matching the tightened verifier range [0,1]. Co-Authored-By: Claude <noreply@anthropic.com>

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[LLVM][FlyDSL] Bump up LLVM and Adapt FlyDSL to upstream LLVM/MLIR API changes - #945

[LLVM][FlyDSL] Bump up LLVM and Adapt FlyDSL to upstream LLVM/MLIR API changes#945
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jli-melchior commented Jul 31, 2026 •

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